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Forum: FPGA, VHDL & Verilog part of a reg as statmeant in case


Author: shmulik (Guest)
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hi all,
can i use part of a bus as statement in case?

for an example:
case ( work_plan(2:0) )
     00 :

and etc'

Author: Lothar Miller (lkmiller) (Moderator)
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Give it a try...

Author: shmulik (Guest)
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well it not wroking for me, so i meant, how should i write it ? should i 
declare a new reg ?

Author: Lattice User (Guest)
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shmulik wrote:
> hi all,
> can i use part of a bus as statement in case?
>
> for an example:
> case ( work_plan(2:0) )
>      00 :
>
> and etc'

This should work.
If there is something wrong, it is outside the sample.

Author: shmulik (Guest)
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i wrote :
always @ ( slsrc or sldet )
  begin
    case ( work_plan(2:0) )
      APB_SLAVE1    :
        sone_addr  = sldst;
        sone_we    = 1111;
        sone_wdata  = prdata;


and this is the massge i recive when trying to compile:

...(165): near ":": syntax error, unexpected ':', expecting ')'.

when i deleted it, and wrote:

always @ ( slsrc or sldet )
  begin

    case ( work_plan )
      APB_SLAVE1    :
        sone_addr  = sldst;
        sone_we    = 1111;
        sone_wdata  = prdata;

i recive no error.

Author: Lattice User (Guest)
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Sorry i overlooked a fundamental error in your sample
You need to use square brackets!

Author: shmulik (Guest)
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lol its working, how i didn't see that ?!?!
thanks very much !!!!!!!

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