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Forum: FPGA, VHDL & Verilog Large arrays


Author: Saltwater (Guest)
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I was experimenting with building large arrays, but after a substantial 
compilation time there is hardly a tax on logic. It made me wonder where 
the registers have gone? And ultimately what is wisdom in builing large 
arrays?

Author: Lothar Miller (lkmiller) (Moderator)
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Saltwater wrote:
> I was experimenting with building large arrays, but after a substantial
> compilation time there is hardly a tax on logic. It made me wonder where
> the registers have gone?
First read your post as if the heck you don't know anything about your 
toolchain, your target and your actual problem. To say it short: read it 
as if you were me (or anybody else on the world). Then answer this 
question: is it possible to give a senseful anwer? No? Right!

Let me just assume you use some kind of HDL and you want to target a 
FPGA, then it may be that your huge array has no connection to the 
outer world, and therefore it is just optimized away...

: Edited by Moderator
Author: Saltwater (Guest)
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Im using Verilog on a Cyclone V FPGA, "reg [32:0] Array [0:524287];"
Referencing the array in the main file. And then pointing to it once, 
And instance wire module to point from it.

To try to try what you said out I made the pointers work, but since im 
constrained to the pins, I cant output my 33bit array just yet. Assuming 
it gets optimised out pointing to the register it is pointing to now.. 
So the result is "296 / 32,070 ( < 1 % )"

But.. In general "if it synthesized" correctly would it be feasible to 
bank on using about 4x (32/24) x 524287 of ram on board? And still 
getting away with some DSP?

Author: Lothar Miller (lkmiller) (Moderator)
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Saltwater wrote:
> would it be feasible to bank on using about 4x (32/24) x 524287 of ram
> on board?
Sounds linke some 20MBits. Does your FPGA have so much RAM inside?
Even the biggest Cyclone V seems to have "only" 12MBits...
http://www.altera.com/devices/fpga/cyclone-v-fpgas...

Author: Saltwater (Guest)
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http://www.altera.com/devices/fpga/cyclone-v-fpgas...

I see, it's ~4Mbit for the SE SoC model. It does look great on paper. Ah 
well maybe later I can dedicate the proper hardware to it. Memory 
controller it is then..

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