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Forum: FPGA, VHDL & Verilog LED intensity


Author: Oer Pdw (Company: None) (ponta)
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Hello, I got an assignment to make LED lights change intensity, by 
switching 4 switches on pegasus board. I got some code but I don't think 
it's good. Can you check it or improve it? Thanks


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity PWM is
  generic
  (
    sd        : unsigned(11 downto 0) := X"C35" -- 3125 in hex
  );
  port
  (
    clock     : in   std_logic;
    switches  : in   unsigned(3 downto 0);
    pwm       : out  std_logic
  );
end PWM;
 
architecture behave_PWM of PWM is
  signal counter : unsigned(15 downto 0);
 
begin -- architecture
  pwm_proc: process (clock)
  begin
    if (counter <= switches*sd) then
      pwm <= '1';
    else
      pwm <= '0';
    end if;
 
    if (counter >= 50000) then
      counter <= (others => '0');
    else
      counter <= counter + 1;
    end if;
  end process;
 
end behave_PWM;

Author: Lothar Miller (lkmiller) (Moderator)
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Oer Pdw wrote:
> I got some code but I don't think it's good.
You are right. This will work in a simulator at best. But you will never 
ever get it on hardware.

The major drawback is the missing clock inside the process. It is not 
enough to have the clock in the sensitivity list. Look how all the 
others do it...

: Edited by Moderator
Author: Oer Pdw (Company: None) (ponta)
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The problem is that everyone has different task so I can't check
Can you help me?

Author: Lothar Miller (lkmiller) (Moderator)
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Oer Pdw wrote:
> The problem is that everyone has different task
What should this sentence say?

What I said is: there is no clock in your design! But each counter needs 
a clock because its built of flipflops. Have a look how everybody on the 
world describes a counter. There must be a rising_edge() or a 'event 
in your code!

: Edited by Moderator
Author: Oer Pdw (Company: None) (ponta)
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Is it good now?


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity PWM is
  generic
  (
    sd        : unsigned(7 downto 0) := X"C3" -- 195 in hex
  );
  port
  (
    clock     : in   std_logic;
    switches  : in   unsigned(7 downto 0);
    pwm       : out  std_logic
  );
end PWM;
 
architecture behave_PWM of PWM is
  signal counter : unsigned(15 downto 0);
 
begin -- architecture
  pwm_proc: process (clock)
  begin
if(clock'event and clock='0'") then
    if (counter <= switches*sd) then
      pwm <= '1';
    else
      pwm <= '0';
    end if;
 
    if (counter >= 50000) then
      counter <= (others => '0');
    else
      counter <= counter + 1;
end if;
    end if;
  end process;
 
end behave_PWM;


Author: Lothar Miller (lkmiller) (Moderator)
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Oer Pdw wrote:
> Is it good now?
There is a syntax error in it, but the concept is ok.

> Is it good now?
Take a little test bench and check it out...

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