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Open Source VHDL Verification Methodology(OSVVM)
von SparkyT (Guest)

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Hi to everyone,
I have beem reading for a bit about OSVVM, the Open Source VHDL 
Verification Methodology. I found it very interesting, although i have 
major issues understanding it. Can anyone explain in a few words how to 
start with it?

ps. some examples that i found

http://www.edaplayground.com/x/49J
https://gist.github.com/tmeissner/1ca16372e247098d9462
https://www.aldec.com/en/company/blog/71--my-first-example-with-os-vvm-coveragepkg

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Re: Open Source VHDL Verification Methodology(OSVVM)
von Jim Lewis (Guest)

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I recommend that you start with the user guides that are in the download 
- specifically CoveragePkg_user_guide.pdf and RandomPkg_user_guide.pdf.

You can get the latest download at:
http://www.osvvm.org/downloads

You will need to create an account to get to the downloads page.

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