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Forum: FPGA, VHDL & Verilog help regarding UART Xilinx IP


Author: Ananya Devraj (Company: Aseema Softnet) (a_devraj)
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Can anybody please help me in figuring out the Xilinx uart and CORDIC 
(4.0) IPs ? (Finding the official doc a bit difficult to understand)

Author: Lothar Miller (lkmiller) (Moderator)
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Your question is unclear. Could you ask a bit more specific?

Author: Ananya Devraj (Company: Aseema Softnet) (a_devraj)
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First narrowing down to uart,

I am trying to simulate "XAPP341(verilog)" IP of Xilinx in ISE 14.5.

But am unable to enable/provide propper signal inputs through the 
testbench. Due to this the output data(dout) is not equal to the input 
data(din).
Or, for that matter am able to get only Z/zero value for dout.

Is this info enough?

do i need to explain the XAPP341 Rx & Tx consideration?


Thanks & regards,
Devraj

Author: Lothar Miller (lkmiller) (Moderator)
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Ananya Devraj wrote:
> Or, for that matter am able to get only Z/zero value for dout.
Z is not 'zero'.
Z is 'high impedance'.
Usually that is the output port value of a disabled component on a 
bus...

> But am unable to enable/provide propper signal inputs through the
> testbench.
What signals do you provide?

> Is this info enough?
No.
Show your testbench and the waveform. Say what you expect and what you 
get instead. Read your post as if you know nothing of your problem. We 
all here do not know anything about your specific problem. I had to ask 
back for a little slice of information: it in your second post we found 
out about your HDL and the version of the uart core. Apply as much 
infomation as necessary to make your problem understandable to someone 
else...

: Edited by Moderator
Author: Ananya Devraj (Company: Aseema Softnet) (a_devraj)
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Attached files:

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Since, it was my 1st post in the forum, it was unclear. Sorry for my 
unclear queries posted earlier.
Highly appreciate all your replies.

I meant :
am able to make the output dout as z (high imp.) or get zero value with 
the help of the reset signal (rst) in the design.

UART input signals:
1]. clock  (clk16x)
2]. reset  (rst)
3]. data in (din : 8 bit)
4]. wrn (control signal which stobes the data from din to tbr, which is 
a internal signal in Tx )
5]. rxd (input signal to rx)
6]. rdn (read strobe)


Have attached the verilog design files ( rar format )

The design file consists of separate receiver (rcvr & rcvr_tf) and 
transmitter (txmit & txmit_tf) instantiation modules.

These receiver and transmitter modules has to be instantiated inside the 
uart module ( uart ).
after this, used uart_tb file to run the simulation.

Tried giving 8 bit 1's as input ( @ din) along with other inputs (is 
specified in design testbench file), but getting zero output ( @ dout) 
instead.

Expected output : (data input - 8 bit) din = dout (data output - 8 bit)

regards,
Devraj

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