# Forum: FPGA, VHDL & Verilog Counter Design with D Flip-Flop

 Author: Cemal Unal (Company: Hacettepe University) (cemal) Posted on: 2014-12-29 13:41

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I will write a counter code in verilog that counts like this
(with D Flip Flop and some logic gates)

0000 -> 0
0010 -> 2
0100 -> 4
0110 -> 6
1000 -> 8
1010 -> 10
1100 -> 12
1001 -> 9
0110 -> 6
0011 -> 3
0000 -> 0

Can someone help me how I can write it ?  :) thanks

 Author: Lothar Miller (lkmiller) (Moderator) Posted on: 2014-12-30 12:27

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Cemal Unal wrote:
> Can someone help me how I can write it ?  :)
What comes after the ending '0'?

If the counter loops again from the beginning, then implement a counter
that counts in cycles from 0 to 9 and decode each counter step to your
desired output value afterwards:
 reg [3:0] cnt = 4'h0; always @ (posedge clock) begin : COUNTER if (cnt < 9) cnt <= cnt + 1; else cnt = 4'h0; end always @ (cnt) begin : DECODER case (cnt) 4'h0: out = 4'b0000; 4'h1: out = 4'b0010; 4'h2: out = 4'b0100; : 4'h9: out = 4'b0011; endcase end 

And so you don't have to dig around with D-FFs and logic gates. The
synthesizer/compiler has to deal with it...

 Author: Ale (Guest) Posted on: 2014-12-30 12:49

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Lothar wrote a behavioral description of what you wanted... but you
could write it using  primitives (d-flipflops and gates) to achieve the
same result... as you wanted... You may wan to draw the circuit on a
piece of paper, or you could use the schematic editor that some fpga
packages provide

 Author: Cemal Unal (Company: Hacettepe University) (cemal) Posted on: 2014-12-30 14:39

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Lothar and Ale thanks a lot for your answers..

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