Forum: FPGA, VHDL & Verilog Memory issues

Author: Compstomp (Guest)
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Altera forum is dead as ever on this issue.. I have a DDR3 controller, 
but in order to test it i have to get the Quartus to interface to my 
DDR3 stick. As in connect the physical pins to my project. This it does 
not do for some reason I cant really put my finger on. But I get "those" 
warnings. Could this be due to termination IE can be ignored or?

Error (14566): Could not place 2 periphery component(s) due to conflicts 
with existing constraints (2 pin(s))

  Error (175020): Illegal constraint of pin to the region (89, 69) to 
(89, 80): no valid locations in region

    Info (14596): Information about the failing component:
      Info (175028): The pin name: WE // Write enable
    Info (14597): No legal location could be found for this component 
out of 1 considered location(s).  Reasons why each location could not be 
used are summarized below:
      Error (184016): There were not enough single-ended output pin 
locations available (1 location affected)
        Info (175029): C28 // Exists
      Info (175015): The I/O pad WE is constrained to the location 
PIN_C28 due to: User Location Constraints (PIN_C28)
        Info (14709): The constrained I/O pad is contained within this 


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