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Forum: FPGA, VHDL & Verilog CIC filter decimator on VHDL


Author: Dmtry Karlin (Company: stc) (desmond_breezey)
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Hi to all again.
It is a structure with 2 steps : CIC filter decimator and FIR after CIC.

A simulation shows nothing signals on out bus of the structure. I have 
no some ideas why. Can someone say what happening?

: Edited by User
Author: Lothar Miller (lkmiller) (Moderator)
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Dmtry Karlin wrote:
> A simulation shows nothing signals on out bus of the structure
Of course it schows something! What? A 'U' known as "uninitialized"?

> I have no some ideas why.
When you use a reset signal to assign start values (instead of 
initilizing them at the declaration), then you must assert this reset 
signal at the beginning of your test bench...

> I have no some ideas why.
With the simulator you can dig into each signal of each module. Then 
you can easily see, whats going on and whats going wrong...

: Edited by Moderator
Author: Dmtry Karlin (Company: stc) (desmond_breezey)
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Lothar Miller wrote:
> then you must assert this reset
> signal at the beginning of your test bench...

I did it so:

  signal reset : std_logic :='1' ;

  res: process
  begin
  for i in 0 to 100 loop
  wait until clk='1' and clk'event;
  end loop;
  reset <='0';wait;
  end process res;

Also, i created a new output signal (it is called trans).
 trans <= transfer 
,
transfer - a signal with information from output bus of CIC. In the 
simulator i saw that trans have status "U", and on output bus i have 
nulls. What is it mean? Is the CIC wrong? But i took an example from the 
book, and FIR filter also must be done correctly, because i did FIR some 
times ago and it was done correctly, and i just have taken my previous 
code with the necessary changes.

: Edited by User
Author: Dmtry Karlin (Company: stc) (desmond_breezey)
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Oh, i understood.

I think you mean somethink like this:
signal filter_in : std_logic_vector(7 downto 0):= (others =>'0');

: Edited by User

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