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Forum: FPGA, VHDL & Verilog Seven Segment Display design with 2 4-1 MUXes


von Keith F. (Guest)


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I am a tad bit lost with going about how to code this. I was given 2 
types of code to help me with this design but I'm lost at coding the 2 
4-1 MUXes into the SSeg decoder. Any help is greatly appreciated!


Here is the provided coding I was given:
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//Hex to SSeg LED decoder
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module hex_to_sseg
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   (
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    input wire [3:0] hex,
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    input wire dp,
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    output reg [7:0] sseg  // output active low
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   );
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   always @*
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   begin
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      case(hex)
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         4'h0: sseg[6:0] = 7'b0000001;
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         4'h1: sseg[6:0] = 7'b1001111;
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         4'h2: sseg[6:0] = 7'b0010010;
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         4'h3: sseg[6:0] = 7'b0000110;
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         4'h4: sseg[6:0] = 7'b1001100;
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         4'h5: sseg[6:0] = 7'b0100100;
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         4'h6: sseg[6:0] = 7'b0100000;
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         4'h7: sseg[6:0] = 7'b0001111;
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         4'h8: sseg[6:0] = 7'b0000000;
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         4'h9: sseg[6:0] = 7'b0000100;
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         4'ha: sseg[6:0] = 7'b0001000;
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         4'hb: sseg[6:0] = 7'b1100000;
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         4'hc: sseg[6:0] = 7'b0110001;
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         4'hd: sseg[6:0] = 7'b1000010;
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         4'he: sseg[6:0] = 7'b0110000;
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         default: sseg[6:0] = 7'b0111000;  //4'hf
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     endcase
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     sseg[7] = dp;
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   end
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endmodule
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//4-1 Mux
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module mux( select, d, q );
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input[1:0] select;
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input[3:0] d;
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output q;
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reg q;
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wire[1:0] select;
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wire[3:0] d;
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always @( select or d )
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begin
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   if( select == 0)
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      q = d[0];
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   if( select == 1)
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      q = d[1];
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   if( select == 2)
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      q = d[2];
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   if( select == 3)
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      q = d[3];
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end
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endmodule

von Lothar M. (Company: Titel) (lkmiller) (Moderator)


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Keith F. wrote:
> Here is the provided coding I was given:
And what did you do yourself already? No one here is intended do do 
all of your homework...

> but I'm lost at coding the 2 4-1 MUXes into the SSeg decoder. Any help
> is greatly appreciated!
Thats the way it works: show your try and tell clearly whats the problem 
with it.

At least you musthave a sketch (on a piece of paper) how you would 
conntect those parts given. Then you can easily recognize, whats 
/missing/: you lack a counter steadily walking thru these 4 segments...

If you don't know it already: this here is obviously the 
Nibble-To-Segment decoder:
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                  segments:   abcdefg
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         4'h0: sseg[6:0] = 7'b0000001; // 0
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         4'h1: sseg[6:0] = 7'b1001111; // 1
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         4'h2: sseg[6:0] = 7'b0010010; // ....
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         4'h3: sseg[6:0] = 7'b0000110;
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         4'h4: sseg[6:0] = 7'b1001100;
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         4'h5: sseg[6:0] = 7'b0100100;
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         4'h6: sseg[6:0] = 7'b0100000;
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         4'h7: sseg[6:0] = 7'b0001111;
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         4'h8: sseg[6:0] = 7'b0000000;
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         4'h9: sseg[6:0] = 7'b0000100; // 9
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         4'ha: sseg[6:0] = 7'b0001000; // A
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         4'hb: sseg[6:0] = 7'b1100000; // b
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         4'hc: sseg[6:0] = 7'b0110001; // C
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         4'hd: sseg[6:0] = 7'b1000010; // d
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         4'he: sseg[6:0] = 7'b0110000; // E
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         default: sseg[6:0] = 7'b0111000;  // F
And with the other code snippet you can obviously select one value out 
of 4, so that leads to the assumption, that you have 4 digits to 
display...

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