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Forum: FPGA, VHDL & Verilog Seven Segment Display design with 2 4-1 MUXes


Author: Keith F. (Guest)
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I am a tad bit lost with going about how to code this. I was given 2 
types of code to help me with this design but I'm lost at coding the 2 
4-1 MUXes into the SSeg decoder. Any help is greatly appreciated!


Here is the provided coding I was given:
//Hex to SSeg LED decoder
module hex_to_sseg
   (
    input wire [3:0] hex,
    input wire dp,
    output reg [7:0] sseg  // output active low
   );

   always @*
   begin
      case(hex)
         4'h0: sseg[6:0] = 7'b0000001;
         4'h1: sseg[6:0] = 7'b1001111;
         4'h2: sseg[6:0] = 7'b0010010;
         4'h3: sseg[6:0] = 7'b0000110;
         4'h4: sseg[6:0] = 7'b1001100;
         4'h5: sseg[6:0] = 7'b0100100;
         4'h6: sseg[6:0] = 7'b0100000;
         4'h7: sseg[6:0] = 7'b0001111;
         4'h8: sseg[6:0] = 7'b0000000;
         4'h9: sseg[6:0] = 7'b0000100;
         4'ha: sseg[6:0] = 7'b0001000;
         4'hb: sseg[6:0] = 7'b1100000;
         4'hc: sseg[6:0] = 7'b0110001;
         4'hd: sseg[6:0] = 7'b1000010;
         4'he: sseg[6:0] = 7'b0110000;
         default: sseg[6:0] = 7'b0111000;  //4'hf
     endcase
     sseg[7] = dp;
   end

endmodule

//4-1 Mux
module mux( select, d, q );

input[1:0] select;
input[3:0] d;
output q;

reg q;
wire[1:0] select;
wire[3:0] d;

always @( select or d )
begin
   if( select == 0)
      q = d[0];

   if( select == 1)
      q = d[1];

   if( select == 2)
      q = d[2];

   if( select == 3)
      q = d[3];
end

endmodule

Author: Lothar Miller (lkmiller) (Moderator)
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Keith F. wrote:
> Here is the provided coding I was given:
And what did you do yourself already? No one here is intended do do 
all of your homework...

> but I'm lost at coding the 2 4-1 MUXes into the SSeg decoder. Any help
> is greatly appreciated!
Thats the way it works: show your try and tell clearly whats the problem 
with it.

At least you musthave a sketch (on a piece of paper) how you would 
conntect those parts given. Then you can easily recognize, whats 
/missing/: you lack a counter steadily walking thru these 4 segments...

If you don't know it already: this here is obviously the 
Nibble-To-Segment decoder:
                  segments:   abcdefg
         4'h0: sseg[6:0] = 7'b0000001; // 0
         4'h1: sseg[6:0] = 7'b1001111; // 1
         4'h2: sseg[6:0] = 7'b0010010; // ....
         4'h3: sseg[6:0] = 7'b0000110;
         4'h4: sseg[6:0] = 7'b1001100;
         4'h5: sseg[6:0] = 7'b0100100;
         4'h6: sseg[6:0] = 7'b0100000;
         4'h7: sseg[6:0] = 7'b0001111;
         4'h8: sseg[6:0] = 7'b0000000;
         4'h9: sseg[6:0] = 7'b0000100; // 9
         4'ha: sseg[6:0] = 7'b0001000; // A
         4'hb: sseg[6:0] = 7'b1100000; // b
         4'hc: sseg[6:0] = 7'b0110001; // C
         4'hd: sseg[6:0] = 7'b1000010; // d
         4'he: sseg[6:0] = 7'b0110000; // E
         default: sseg[6:0] = 7'b0111000;  // F
And with the other code snippet you can obviously select one value out 
of 4, so that leads to the assumption, that you have 4 digits to 
display...

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