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Forum: FPGA, VHDL & Verilog Syntax Help with Project


Author: Annon (Guest)
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--Baseball Scorekeeper
--STRIKES  
library IEEE; 
use ieee.std_logic_1164.all; 

entity strikes is

port     (button_press        : in std_logic; 
       reset                  : in  std_logic; 
       led_out            : out std_logic_vector (1 downto 0)
      
       ); 
       
end entity; 
architecture strikes_arch of strikes is 
signal tempLED : std_logic_vector (1 downto 0);
begin

  process ( button_press)
    begin 
    
    if reset='1' then tempLED <="00"; 
        elsif rising_edge(button_press) then
          
      
      case tempLED is 
      
      when "00" => tempLED <="01"; 
      when "01" => tempLED <="11"; 
      when "10" => tempLED <="00"; 
      when "11" => tempLED <="00"; 
      when others => tempLED <= "00"; 
        end case; 
    end if;   
  end process; 
led_out <= tempLED;
end strikes_arch;
    

--BALLS
library IEEE; 
use ieee.std_logic_1164.all; 

entity balls is

port     (button_press        : in std_logic; 
       reset             : in  std_logic; 
       led_out            : out std_logic_vector (2 downto 0)
      
       ); 
       
end entity; 
architecture balls_arch of balls is 
signal tempLED : std_logic_vector (2 downto 0);
begin

  process ( button_press)
    begin 
    
    if reset='1' then tempLED <="000"; 
        elsif rising_edge(button_press) then
          
      
      case tempLED is 
      
      
      when "000" => tempLED <="001"; 
      when "001" => tempLED <="011"; 
      when "010" => tempLED <="000"; 
      when "011" => tempLED <="111"; 
      when others => tempLED <= "000"; 
        end case;
    end if;   
  end process; 
led_out <= tempLED;
end balls_arch; 


library IEEE;
use ieee.std_logic_1164.all; 

entity Baseball is 
port   ( b1, b2, b3    : in std_logic;
      --mst_rst   : in std_logic; 
      strikes   : out std_logic_vector (1 downto 0); 
      balls    : out std_logic_vector (2 downto 0)
      
      ); 

end entity; 

architecture Baseball_arch of Baseball is 
--signal tempStrikes :  std_logic_vector (1 downto 0);
--signal tempBalls   :  std_logic_vector (2 downto 0); 
--signal temprst     : std_logic; 

component strikes is

port     (button_press        : in std_logic; 
       reset                  : in  std_logic; 
       led_out            : out std_logic_vector (1 downto 0)
      
       ); 
end component; 

component balls is

port     (button_press     : in std_logic; 
       reset             : in  std_logic; 
       led_out         : out std_logic_vector (2 downto 0)
      
       ); 

end component; 

begin

  UX0: port map strikes (button_press=> b1, reset=>b3, led_out=>strikes); 
  UX1: port map balls   (button_press=> b2, reset=>b3, led_out=>balls ); 

end Baseball_arch; 


Error:
.
Error (10500): VHDL syntax error at Baseball.vhd(121) near text "port"; 
expecting "(", or an identifier ("port" is a reserved keyword), or a 
sequential statement
Error (10500): VHDL syntax error at Baseball.vhd(122) near text "port"; 
expecting "(", or an identifier ("port" is a reserved keyword), or a 
sequential statement

**The "port" it's referring to is in my port mapping section**
I'm not sure if it has something to do with the internal signals. 
Although, looking at my design on paper the only thing connecting the 
"strikes" and "balls" blocks together is my reset which is just tied to 
an external button (b3). Hmm..it's always something small. I'd 
appreciate a look.

Thanks.

Author: Lothar Miller (lkmiller) (Moderator)
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This will give a wrong simuslation due to a wrong sensitivity list:
 process ( button_press) begin
    if reset='1' then 
       tempLED <="00";
    elsif rising_edge(button_press) then
       ...
And additionally: a button is never(!!!) a clock source. But you will 
see that in real life later on...

But your actual problem is as reported here:
  UX0: port map strikes (
And there:
  UX1: port map balls   (
Check the order of "port map" and "strikes", as well as "port map" and 
"balls"...

: Edited by Moderator
Author: Jay JA (jboss10)
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Thank you Lothar. You are always willing to help. I figured out what was 
wrong and was able to compile. I do understand, in a real-world 
application this should/would never be done, but for the sake of my 
project it suffices.

Question..I'm trying to figure out how to make this work so when the 
baseball count is, let's say, 3-balls and 1-strike. If the next ball is 
thrown is a "ball" then both the strikes and balls LEDs get reset back 
to "00" and "000", respectively.

Do I create another process? Or another entity entirely? I've done it 
almost 10 different ways and none of which have worked or compiled. It's 
tricky trying to get both balls and strikes to get reset when they are 
in totally different processes. I've only been coding in VHDL for maybe 
two months so bare with me.

I appreciate your help. Enjoy the holidays.

**Corrected Code:

--STRIKES  
library IEEE; 
use ieee.std_logic_1164.all; 

entity strike is

port     (button_press        : in std_logic; 
       reset                  : in  std_logic; 
       led_out            : out std_logic_vector (1 downto 0)
      
       ); 
       
end entity; 
architecture strike_arch of strike is 
signal tempLED : std_logic_vector (1 downto 0);
begin

  process ( button_press)
    begin 
    
    if reset='1' then tempLED <="00"; 
        elsif rising_edge(button_press) then
          
      
      case tempLED is 
      
      when "00" => tempLED <="01"; 
      when "01" => tempLED <="11"; 
      when "10" => tempLED <="00"; 
      when "11" => tempLED <="00"; 
      when others => tempLED <= "00"; 
        end case; 
    end if;   
  end process; 
led_out <= tempLED;

end strike_arch;
    

--BALLS
library IEEE; 
use ieee.std_logic_1164.all; 

entity ball is

port     (button_press        : in std_logic; 
       reset             : in  std_logic; 
       led_out            : out std_logic_vector (2 downto 0)
      
       ); 
       
end entity; 
architecture ball_arch of ball is 
signal tempLED : std_logic_vector (2 downto 0);
begin

  process ( button_press)
    begin 
    
    if reset='1' then tempLED <="000"; 
        elsif rising_edge(button_press) then
          
      
      case tempLED is 
      
      
      when "000" => tempLED <="001"; 
      when "001" => tempLED <="011"; 
      when "010" => tempLED <="000"; 
      when "011" => tempLED <="111"; 
      when others => tempLED <= "000"; 
        end case;
    end if;   
  end process; 
led_out <= tempLED;
end ball_arch; 




library IEEE;
use ieee.std_logic_1164.all; 

entity Baseball is 
port   ( b1_strikes, b2_balls, b3_hit    : in std_logic;
      strikes   : out std_logic_vector (1 downto 0); 
      balls    : out std_logic_vector (2 downto 0)
      
      ); 

end entity; 

architecture Baseball_arch of Baseball is 
--signal tempStrikes :  std_logic_vector (1 downto 0);
--signal tempBalls   :  std_logic_vector (2 downto 0); 
--signal temprst     : std_logic; 


  
component strike is

port     (button_press        : in std_logic; 
       reset                  : in  std_logic; 
       led_out            : out std_logic_vector (1 downto 0)
      
       ); 
end component; 

component ball is

port     (button_press     : in std_logic; 
       reset             : in  std_logic; 
       led_out         : out std_logic_vector (2 downto 0)
      
       ); 

end component; 

begin

  UX0: strike port map  (button_press=> b1_strikes, reset=>b3_hit, led_out=>strikes); 
  UX1: ball port map    (button_press=> b2_balls, reset=>b3_hit, led_out=>balls); 

end Baseball_arch; 
  
      

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