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Forum: FPGA, VHDL & Verilog Can I get this to work in Verilog


Author: Astudentofminewhowasalittlepiggie (Guest)
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Hi Like the title says..Can I get this to work in Verilog?

if ((control == 0) and (array == 1) and (value > minvalue) and (value < 
maxvalue))

Author: Lothar Miller (lkmiller) (Moderator)
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Astudentofminewhowasalittlepiggie wrote:
> Can I get this to work in Verilog?
Whats the problem with it? Do you encounter any problems? Which ones?

Author: Astudentofminewhowasalittlepiggie (Guest)
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Yes, its a compiler error.

Error (10170): Verilog HDL syntax error at Graycounter.v(15) near text 
";";  expecting ")"

Author: Astudentofminewhowasalittlepiggie (Guest)
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Ofcourse not that, i needed a recompile..

Error (10170): Verilog HDL syntax error at Graycounter.v(15) near text 
"and";  expecting ")"

this one..

Author: Lattice User (Guest)
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The and operator is written as &&, just like in C

Author: Astudentofminewhowasalittlepiggie (Guest)
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Yes, that compiled. thanks!

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