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Forum: FPGA, VHDL & Verilog Simple 16 bit Arithmetic Unit


Author: Omar Rashad (Guest)
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Hello again, I  have so far wrote and tested the codes for a 16 bit 
adder, and a 16 bit multiplier to be used as components of the AU. I am 
facing a strange error though when compiling the AU code. Here are my 
codes:

Adder:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity FullAdder16Bit is
    Port(A,B: IN std_logic_vector(15 DOWNTO 0);
         Cin: IN std_logic;
         Sum: OUT std_logic_vector(15 DOWNTO 0);
         Cout: OUT std_logic);
end FullAdder16Bit;

architecture behavior of FullAdder16bit is

begin
    process(A,B,Cin)
    variable carry: std_logic;

    begin
    carry:=Cin;
        for i in 0 to 15 loop
        carry:= (A(i) and B(i)) or (carry and (A(i) or B(i)));
        end loop;
    Sum <= A + B + Cin;
    Cout <= carry;
    end process;
end behavior;


Multiplier
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Multiplier16 is
  port (A,B: IN std_logic_vector (15 downto 0);
        Pro: OUT std_logic_vector (31 downto 0));
end Multiplier16;

architecture behavior of Multiplier16 is
begin
  Pro <= A*B;
end behavior;

And finally, the AU:
library ieee;
use ieee.std_logic_1164.all;

entity AU is
  port (A,B: IN std_logic_vector (15 downto 0);
        Opcode: IN std_logic_vector (2 downto 0);
        AU_O: OUT std_logic_vector (31 downto 0));
end AU;

architecture behavior of AU is
component FullAdder16Bit
  port (A,B: IN std_logic_vector (15 downto 0);
        Cin: IN std_logic;
        Sum: OUT std_logic_vector (15 downto 0);
        Cout: OUT std_logic);
end component;

component Multiplier16 is
  port (A,B: IN std_logic_vector (15 downto 0);
        Pro: OUT std_logic_vector (31 downto 0));
end component;

signal Pro: std_logic_vector (31 downto 0):= (others => '0');
signal Sum: std_logic_vector (15 downto 0);
signal Cout: std_logic:= '0';

begin
ADD: FullAdder16Bit port map (A=>A, B=>B, Cin=>'0', Sum=>Sum, Cout=>Cout);
MUL: Multiplier16 port map (A=>A, B=>B, Pro=>Pro);

with Opcode select
  AU_O <= "000000000000000" & Cout & Sum when "000",
          Pro when "001",
          (others => 'Z') when others; 

end behavior;

AU Test Bench:
library ieee;
use ieee.std_logic_1164.all;

entity tb_AU is
end tb_AU;

architecture behavior of tb_AU is
component AU
  port (A,B: IN std_logic_vector(15 downto 0);
        Opcode: IN std_logic_vector(2 downto 0);
        AU_O: OUT std_logic_vector(31 downto 0));
end component;

signal A,B: std_logic_vector(15 downto 0);
signal Opcode: std_logic_vector(2 downto 0);
signal AU_O: std_logic_vector(31 downto 0);

begin
DUT: AU port map (A=>A,B=>B,Opcode=>Opcode,AU_O=>AU_O);

process
begin
wait for 0 ns;
A <= x"0001"; B <= x"FFFF"; Opcode <= "000";
wait for 10 ns;
Opcode <= "001";
wait for 10 ns;
end process;
end behavior;

configuration tb_AU_con of tb_AU is
for behavior
end for;
end tb_AU_con;

When trying to simulate with vcs, I get this error:
Error -- [BADFORMALSPEC] Bad Formal Part Specified'
formal port 'PRO' in component Multiplier16 (AU.vhd:18) cannot be found 
in entity Multiplier16 (Multiplier16.vhd:6)

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:
Attached files:

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First:
When you write that:       Pro <= A*B;
Why don't you write that:  Sum <= A+B;

Omar Rashad wrote:
> Error -- [BADFORMALSPEC] Bad Formal Part Specified' formal port 'PRO' in
> component Multiplier16 (AU.vhd:18) cannot be found in entity
> Multiplier16 (Multiplier16.vhd:6)
Something with your project configuration is wrong. With ISIM its 
working fine...

You can skip this last four lines without any problems:
> configuration tb_AU_con of tb_AU is
> for behavior
> end for;
> end tb_AU_con;

Author: Omar Rashad (Guest)
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Well I do have sum<= a + b + cin in the adder SC. But im also 
calculating the cout with the process. Anyway, that shouldnt affect the 
code since the adder was tested successfully.

Are you saying there is nothing wrong with my code? Should removing the 
last four lines make it work? We are forced to use vcs for simulation...

Author: Omar Rashad (Guest)
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Problem solved. I just created a new directory and moved all the files 
to it and re compiled and simulated. Works fine! Thanks!

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