EmbDev.net

Forum: FPGA, VHDL & Verilog Using the Xilinx ISE Design Suite 14.7 version


Author: Juan (Guest)
Posted on:
Attached files:

Rate this post
0 useful
not useful
I am using a Xilinx Spartan 3E-100 Basys2 module in order to make a 
design corresponding to a dynamic display circuit into the ISE design 
suite program (14.7 version), however when generating the program file, 
when I start to make a synthesis of the main program and its modules it 
returns me two errors and It says that one of them corresponds to the 
part of implementation of design, and the other to the translation of 
the program. If someone could help me find out why this happens or what 
would be the typical reasons why such errors occur, it would be really 
helpful.

Author: Björn Punkt (bjrn_g)
Posted on:

Rate this post
0 useful
not useful
Can you reply the error code please?!
It is impossible so make a remote diagnostics without knowing the full 
project or the error code.

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:
Attached files:

Rate this post
0 useful
not useful
Juan wrote:
> why such errors occur
Which one? What do you see on the "Errors" tab?

Author: Juan (Guest)
Posted on:

Rate this post
0 useful
not useful
Yes, the one that is on the "Errors" tab. Also the ones that are 
highlighted on the image.

Author: please (Guest)
Posted on:

Rate this post
0 useful
not useful
klick on the Error tab, so everyone (including you) sees the actual 
error description.

And maybe you first work through some ISE Tutorials sometime...

Author: Juan (Guest)
Posted on:

Rate this post
0 useful
not useful
Forgive me for the response again, well about the error it actually 
says:

"#3/Dinamico/dinamico.ucf(22)]: NET "btn<3>" not found. Please verify 
that: 1. The specified design element actually exists in the original 
design. 2. The specified object is spelled correctly in the constraint 
source file".

Author: please (Guest)
Posted on:

Rate this post
0 useful
not useful
Juan,
Obviously you're lacking fundamental knowledge of FPGA development. You 
should find Demo-Projects for your Xilinx Spartan 3E-100 Basys2 module 
and use these to learn what's going on in .ucf files, during Synthesize, 
Translate, Map, Place&Route,...
Your (current) error is, that your .ucf file tries to constrain a signal 
called btn<3> (probably to a PIN location or maybe a timing net). But 
such a signal (wire) does not occur in your code (i.e. input/output 
list)

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.