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Forum: FPGA, VHDL & Verilog Display 640x480 Nexys 3 board


Author: sketchy (Guest)
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I've been trying to display something with a vga. I wanted a signal 640 
x 480 @ 60 Hz.
So what I have so far in my code: Implemented the clk signal, the red, 
blue, green, hsync and vsync. Using a Clocking Wizard I made the 
25.175MHz needed from 100MHz(nexys 3 board) then the hcounter and 
vcounter but this is where I get lost, when I have to asign the 1's  to 
all RGB signals I kinda don't know where I need to use it to make it 
work.

Also the timing I got it from here 
http://tinyvga.com/vga-timing/640x480@60Hz

.ucf
--------------------------------------------------------
NET "clk" LOC = V10;

NET "red[0]" LOC = U7;
NET "red[1]" LOC = V7;
NET "red[2]" LOC = N7;

NET "green[0]" LOC = P8;
NET "green[1]" LOC = T6;
NET "green[2]" LOC =  V6;

NET "blue[1]" LOC = R7;
NET "blue[2]" LOC = T7;


NET "Hsync" LOC = N6;
NET "Vsync" LOC = P7;
--------------------------------------------------------

.vhd
---------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity vgax is
    Port ( clk : in  STD_LOGIC;
           Hsync : out  STD_LOGIC;
           Vsync : out  STD_LOGIC;
           red : out  STD_LOGIC_VECTOR (2 downto 0);
           green : out  STD_LOGIC_VECTOR (2 downto 0);
           blue : out  STD_LOGIC_VECTOR (2 downto 1));
end vgax;

architecture Behavioral of vgax is
COMPONENT dcmx
port(CLK_IN1 : in std_logic;
    CLK_OUT1 : out std_logic);
END COMPONENT;

signal clk25M : std_logic;
signal hcounter : std_logic_vector(9 downto 0) := (others => '0');
signal vcounter : std_logic_vector(9 downto 0) := (others => '0');

begin
Inst_dcmx: dcmx PORT MAP(
     CLK_IN1 => clk,
     CLK_OUT1 => clk25M
);

--process(hcounter,vcounter)
--end process;

process(clk25m)
   begin
  ------------------------------------------
     if clk25M'event and clk25M = '1' then
       if hcounter = 799 then
         hcounter <= (others => '0');
         if vcounter = 524 then
           vcounter <= (others => '0');
         else
           vcounter <= vcounter+1;
         end if;
       else
         hcounter <= hcounter+1;
       end if;
  ---------------------------------------  
  
    ----------------------
    if hcounter > 656 and hcounter < 752 then
    hsync<='0';
    else
    hsync<='1';
    end if;
  
    if vcounter > 490 and vcounter < 491 then
    vsync <='0';
    else 
    vsync <='1';
    end if;
    ------------------------------------
    --He I want to make it always display the white colour 
    ---------------------------------------
    if hcounter < 640 and vcounter < 480 then
    red<= "111";
    green<="111";
    blue<="11";
    hsync<='1';
    vsync<='0';
    else
    red<= "111";
    green<="111";
    blue<="11";
    hsync<='1';
    vsync<='0';
    end if;
    -------------------------------------------
    
    
    end if;
end process;

end Behavioral;
---------------------------------------------------------




The result of this is nothing displayed at the screen.

Author: Lothar Miller (lkmiller) (Moderator)
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sketchy wrote:
> The result of this is nothing displayed at the screen.
What does the simulation show?
Do you have a scope to measure the signals?

> Using a Clocking Wizard I made the 25.175MHz needed from 100MHz(nexys 3
> board)
And does it work correctly? Do you get the desired 25MHz? If you don't 
have a scope just count to 12500000 and toggle a LED. It should flash 
each second...
BTW: it would be slightly easier to only generate a 25MHz clock enable 
out of the 100MHz. The VGA will cope up with that slight deviation...

Why that:
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
With this you may have some kind of strange errror messages due to 
double definitions of data types. Use the numeric_st alone. And use 
integer for counters!

Author: sketchy (Guest)
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Lothar Miller wrote:
> What does the simulation show?
> Do you have a scope to measure the signals?

No I don't have it.

Lothar Miller wrote:
> BTW: it would be slightly easier to only generate a 25MHz clock enable
> out of the 100MHz. The VGA will cope up with that slight deviation...

How I'm supposed to do this?

Lothar Miller wrote:
> Why that:use IEEE.NUMERIC_STD.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
> With this you may have some kind of strange errror messages due to
> double definitions of data types. Use the numeric_st alone. And use
> integer for counters!

To be able to do numeric operations on STD_LOGIC_VECTOR signals.

I don't have much reference, just my nexys 3 manual to follow, I'm 
trying to figuring it out how to make it on my own but it would be nice 
you could provide me some reference links. I'm very new with VHDL.

Author: Lothar Miller (lkmiller) (Moderator)
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sketchy wrote:
> To be able to do numeric operations on STD_LOGIC_VECTOR signals.
Don't do calculations with unconstrained std_logic_vectors! Never!!
You don't know, what number a bit pattern in a std_logic_vector 
represents! For example: what number is this "1001" here? Is it 9 or is 
it -7? Both of them are right. Its just a different interpretation of 
that bit pattern.

So use the numeric_std and the integer data type for counters. Or at 
least the unsigned data type...

> I'm very new with VHDL.
Did you do the flashing light and the cahsing light already? Do you 
simulate your designs? If "No" for either case, then do it!

Try Google translator, its German:
http://www.lothar-miller.de/s9y/archives/80-Hello-...
http://www.lothar-miller.de/s9y/archives/61-Lauflicht.html
http://www.lothar-miller.de/s9y/archives/81-Xilinx...

sketchy wrote:
>> generate a 25MHz clock enable out of the 100MHz.
> How I'm supposed to do this?
See the Hello-World code above. Theres a clock divider generating a 
clock enable inside.

Author: peter (Guest)
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Der Ausländer möchte kein Lauflicht, der möchte das sein VGA-Gebilde ein 
Bild anzeigt was er gebastelt hat.

Immer diese Lauflichter...das bringt doch nichts, ist nur 
Zeitverschwendung mit so einem Zeugs weiterzuhelfen, das kannst du da 
einstampfen.

Gruss

Author: -gb- (Guest)
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There are 800x600 with 50MHz and 1024x768 with 75MHz.

Author: peter (Guest)
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Hier..., aber nicht nach China schicken...
Ist für eine DE0/DE1, kannste auch für dich umstricken.
VGA 640x480.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;

entity vga_timing1 is
port(
  clk50_in  : in std_logic;
  hs_out    : out std_logic;
  vs_out    : out std_logic;
  
  red_out   : OUT STD_LOGIC_VECTOR(3 downto 0);
  green_out : OUT STD_LOGIC_VECTOR(3 downto 0);
  blue_out  : OUT STD_LOGIC_VECTOR(3 downto 0)
  ); 
end vga_timing1;

architecture behavioral of vga_timing1 is

signal clk25    : std_logic:='0';
signal hcounter : integer := 0;
signal vcounter : integer := 0;

begin

process (clk50_in)
begin
  if rising_edge(clk50_in) then
    clk25 <= not clk25;
  end if;
end process;

process (vcounter,hcounter)
begin
  if vcounter<480 then
    if (hcounter >=  0 and hcounter <= 160) then
      red_out<="1000";
    else
      red_out<="0000";
    end if;
    
    if (hcounter >= 160 and hcounter <= 320) then
      green_out<="1000";
    else
      green_out<="0000";
    end if;
    
    if (hcounter >= 320 and hcounter <= 480) then
      blue_out<="1000";
    else
      blue_out<="0000";
    end if;  
    
    if (hcounter >= 480 and hcounter <= 640) then
      red_out<="1000";
      green_out<="1000";
      blue_out<="1000";
    end if;
  end if;
end process;

process (clk25)
begin
  if rising_edge(clk25) then
    if hcounter >= (639+16) and hcounter <= (639+16+96) then
      hs_out <= '0';
    else
      hs_out <= '1';
    end if;
  
    if vcounter >= (479+10) and vcounter <= (479+10+2) then
      vs_out <= '0';
     else
      vs_out <= '1';
    end if;
  
--- horizontal counts from 0 to 799
    hcounter <= hcounter+1;
  
    if hcounter = 799 then
      vcounter <= vcounter+1;
      hcounter <= 0;
    end if;
  
--- vertical counts from 0 to 524
    if vcounter = 524 then 
      vcounter <= 0;
    end if;
  end if;
end process;

end behavioral;

Author: -gb- (Guest)
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Peter, es gibt hier zwei Möglichkeiten:

- Man kann eine fertige Lösung geben.
- Man kann dem Fragenden Hilfen geben, dass er das Problem selber lösen 
kann.

Vielleicht sollte man den Fragenden fragen was er will. Hier wird 
meistens so geantwortet, dass der Fragende auch etwas lernt. Will man 
eine Hardwarebeschreibungssprache lernen, dann geht das eben bei ganz 
einfachen Dingen los wie der blinkenden LED und dem Lauflicht.

Auch wenn du jetzt zwar ein Bild ausgeben kannst, hast du trotzdem noch 
kein VHDL gelernt und wirst andere sogar leichtere Aufgaben nicht ohne 
Hilfe lösen können.

Ich habe auch zu Beginn mit Vektoren gerechnet, aber das war ein 
Holzweg. Das hat mir damals auch Lothar gesagt.

Author: Lothar Miller (lkmiller) (Moderator)
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-gb- wrote:
> Vielleicht sollte man den Fragenden fragen was er will.
Und vor Allem auf ENGLISCH.
@peter: Dies hier ist nicht umsonst die englische Abteilung des Forums!! 
Wenn du kein Englisch kannst, oder es nicht verwenden willst, dann lass 
hier die Finger raus. Ich werde in Zukunft jeden dieser ignoranten Posts 
hier löschen.

@all:
peter is one of the little obtrusive mannerless guys here. I told him to 
do any futher conversation in English. Otherwise I will delete those 
ignorant posts.

peter wrote:
> process (clk50_in)
> begin
>   if rising_edge(clk50_in) then
>     clk25 <= not clk25;
>   end if;
> end process;
This ist NO WAY to generate a CLOCK. Read the warnings and infos of the 
synthesis tool!

Clocks are generated either by a clock manager, or the easier way: by 
clock enables. The easiest design on a FPGA has exactly 1 clock. And the 
rest is done by clock enables...

peter wrote:
> Der Ausländer möchte kein Lauflicht, der möchte das sein VGA-Gebilde ein
> Bild anzeigt was er gebastelt hat.
Peter, I can read and understand English very well. And I see, what 
sketchy WANTS, but also I must tell him some words about the "better 
way". You throw a piece of code to him without the faintest hint, what 
this snippet does (I know it very well, you got it to 90% from me! 
Remember?). And then you did not even correct the problem with the clock 
generation...

: Edited by Moderator

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