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VHDL code to implement a SATA disk controller on a Virtex 5 FPGA
von Sunayana C. (sunayana_c)

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Hello All,

I am new to designing a VHDL code for a SATA device. I would like to get 
a few VHDL examples to design the same. Can someone help?

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Re: VHDL code to implement a SATA disk controller on a Virtex 5 FPGA
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Sunayana C. wrote:
> I am new to designing a VHDL code
Then start with the flashing LED, the chasing light, RS232, VGA and so 
on. And half a year later you will be able to do bigger steps...

But you will never get the thing running just by copying some code grime 
somewhere without knowing a thing about hardware.

> for a SATA device.
What hardware (FPGA, ASIC)?
What kind of device?

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Re: VHDL code to implement a SATA disk controller on a Virtex 5 FPGA
von Sunayana C. (sunayana_c)

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I will be using FPGA Virtex 5. I am not copying fyi. I just need some 
examples on how to go about this entire process. Please help if you can

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Re: VHDL code to implement a SATA disk controller on a Virtex 5 FPGA
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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One thing is sure: with no knowledge in VHDL and FPGA you will not be 
able to do the SATA core from scratch the next half year (at least!).
What is your time schedule for this task?
Do you have the money to use a commercial and proved SATA IP core?

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Re: VHDL code to implement a SATA disk controller on a Virtex 5 FPGA
von Sunayana C. (sunayana_c)

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I have experience working on VHDL and FPGA. I have worked on it for an 
year now. I am new to SATA controller. I read through the basics of 
SATA. I now need to know how to write an FPGA code for the same. Please 
provide some examples for the same.

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Re: VHDL code to implement a SATA disk controller on a Virtex 5 FPGA
von blablablub (Guest)

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what examples do you need? SATA is a big and complex protocol. You have 
to consider several levels of protocols.

The first questions is not, if you read the full specification, the 
question is how often you read it?

Then you have to find out the lowest level protocol. Often called as 
physical layer coding or line coding. This is the first step to 
implement.

Then you have to go step by step.


You wrote you have experience in FPGA. Do you also have experience with 
gigabit transceivers? If not, than spend the next month only in 
designing and working with this transceivers. There are a lot of 
pitfalls ...


A simple example code for SATA won't be available, because it is too 
complex. If you don't know how to start, then search for another project 
you can do, where you can collect more experience ...

Cheers

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