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Forum: FPGA, VHDL & Verilog Comparator 2 Bit Question


Author: AOG (Guest)
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Hello to Everybody

Well im new in VHDL so maybe this is a really easy question for some 
people in here i need to do a 2 bit Comparator in Behaviour
mi Design vhdl is like this:



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity comparator_2bit is
     port(
         A : in STD_LOGIC_VECTOR(1 downto 0);
         B : in STD_LOGIC_VECTOR(1 downto 0);
         Igual : out STD_LOGIC;
         Mayor : out STD_LOGIC;
         Menor : out STD_LOGIC
         );
end comparator_2bit;

architecture comparator_2bit_arc of comparator_2bit is
begin

    Igual <= '1' when (a=b) else //EQUALS
             '0';

    Mayor <= '1' when (a<b) else //GRETER
               '0';

    Menor <= '1' when (a>b) else //LOWER
             '0';


end comparator_2bit_arc;

But my question is i don't know how to do the Testbench because i tried 
doing something like this but when i try to compile i have a lot of 
errors

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity comparator_2bit is
port (
         A : in STD_LOGIC_VECTOR(1 downto 0);
         B : in STD_LOGIC_VECTOR(1 downto 0);
         Igual : out STD_LOGIC;
         Mayor : out STD_LOGIC;
         Menor : out STD_LOGIC
     );
end comparator_2bit;

architecture Behavioral of comparator_2bit is
begin
process(a,b)
begin
    A <= '1';
    B <= '1';
    wait for 1 ns;
    assert(Igual='1') report "Fail 1/1" severity error;

    -- Clear inputs
    A <= '0';
    B <= '0';
end process;

end Behavioral;


So please can you help me Im new in VHDL :/

Author: Dussel (Guest)
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Spanish or portuguese VDHL? Sound funny when I read the code in my mind 
:-D

First thing I see is that you use wrong comment style. Comments in VHDL 
are initiated with -- instead of //.

What is the second code supposed to do? The name suggests that it is 
another form of the comparator, but it only assigns values to the 
inputs, which is not allowed and does not make sense in this context.

It would help, if you tell us which errors you get.

Author: AOG (Guest)
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Hey Dussel! Thanks for your reply well those comments with // was only 
in this text edit but well i start moving my code and now it compiles 
but when i see the simulation A and B marks me with "X" when in the 
Testbench im putting 1 or 0

Show you my code:

DESIGN:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity comparator_2bit is
     port(
         A : in std_logic;
         B : in std_logic;
         Igual : out STD_LOGIC;
         Mayor : out STD_LOGIC;
         Menor : out STD_LOGIC
         );
end comparator_2bit;

architecture comparator_2bit_arc of comparator_2bit is
begin

    Igual <= '1' when (a=b) else
             '0';

    Mayor <= '1' when (a<b) else
               '0';

    Menor <= '1' when (a>b) else
             '0';


end comparator_2bit_arc;

TESTBENCH:

library IEEE;
use IEEE.std_logic_1164.all;

entity comparator2bit_TB is
end comparator2bit_TB;

architecture comparator2bit_TB of comparator2bit_TB is

component comparator_2bit is
port(
      A : in std_logic;
         B : in std_logic;
         Igual : out STD_LOGIC;
         Mayor : out STD_LOGIC;
         Menor : out STD_LOGIC);

end component;

signal A,B: std_logic;
signal Igual,Mayor,Menor:std_logic;

begin
DUT: comparator_2bit port map (A,B,Igual,Mayor,Menor);
process
begin

A<='1';
B<='1';
wait for 1 ns;
assert(Igual='1') report "Failed en 0000+0000+0" severity error;

end process;
end comparator2bit_TB;

WHEN I SEE THE SIMULATION SHOWS ME THIS

Author: Dussel (Guest)
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Sorry, I can not see what's wrong.

What happens if you initialise A and B with different values, for 
example A=0, B=1?

My guess is, that your simulator does not run your testbench but your 
comparator as simulation entity. The A and B are not initialised in the 
entity so they have the state 'X'. Then they are bot equal and your 
comparator outputs Igual.

Author: AOG (Guest)
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You were right Dussel Thanks the simulator was running the Design not 
the testbench thank you so much :)

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