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Forum: FPGA, VHDL & Verilog Verilog Code Help


Author: Navtej Johal (Company: RMIT) (johal_navtej)
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Hi
Is there anyone on this forum who can help me write a verilog program 
for a stopwatch. I need it within the next two days to pass my subject. 
I am attaching the problem sheet. This is a completely new language for 
me and if anyone out there can help it would be much appreciated.

I need  to design a stopwatch with three input buttons
button1:start/stop
button2:reset
button3:lap

And n display output of hh mm ss(hours minutes seconds)
hours go from 0-99
minutes 0-59
seconds 0-59

Author: Lothar Miller (lkmiller) (Moderator)
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Navtej Johal wrote:
> I need it within the next two days to pass my subject
Thats not the way things work here!
Let's try it the other way: you show us what you have and tell us about 
particular problems. THEN we can discuss that problems. But no one is 
intended to do your homework (which you have laying around at least 
days...).

BTW: did you read the last sentence on that sheet?

And: Did you try Google?
http://www.google.com/search?q=stop+watch+verilog

Author: Pratik Kulkarni (Company: Rv-VLSI) (pratik_sk)
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Hey hello,
I have a problem here!
A am designing 4:1 mux using 2:1 (Structural).
In 2:1 mux I have written like this,

module mux2to1(y,i,s);
input [1:0] i;

I am using this as a instance in 4:1 prog,
where I am giving inputs as

wire sig1,sig2;
mux2to1 u1(y,sig1,sig2,s0);

Error is : Too many port connections. Expected 3, found 4.

It means thing is that 'i' input in mux 2:1 is recognized as a single 
input by software though I am defining it [1:0] in next line..

Is there any different solution available ?
Or I simply have to do like mux2to1(y,i0,i1,s);

Author: Lattice User (Guest)
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Pratik Kulkarni wrote:
>
> module mux2to1(y,i,s);
> input [1:0] i;
>
> I am using this as a instance in 4:1 prog,
> where I am giving inputs as
>
> wire sig1,sig2;
> mux2to1 u1(y,sig1,sig2,s0);
>
> Error is : Too many port connections. Expected 3, found 4.
>
mux2to1 u1(y, {sig1,sig2}, s0);

Author: Prasanna M. (prasanna_m)
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please help me to write the verilog program for this.

Author: Lothar Miller (lkmiller) (Moderator)
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Prasanna M. wrote:
> please help me to write the verilog program for this.
There is the first step to the solution:
http://embdev.net/topic/342471#3775885

BTW: did you read the thread in front of you?
I am very sure you did not! Because the very SAME exercise and question 
can be found in the FIRST post of this thread!

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