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Forum: FPGA, VHDL & Verilog Illegal recursive instantiation


Author: Iluvatar (Guest)
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Hi guys,

I am having problems with my program and wonder if anyone can help me 
out.
The errormessage i am getting is:
ERROR:HDLCompiler:1171 - Line 30: Illegal recursive instantiation of 
test(rtl)

does anyone know how to solve this?


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
library work;
use work.convert_pack.all;

entity test is --line 30
    Port (
   clk_o : out  STD_LOGIC;
   output : inout std_logic;
   clk : inout std_logic;
   index : inout  std_logic_vector(0 downto 0)

   );
end test;

architecture rtl of test is


    component test
        PORT(
     output  : out std_logic;
     clk : in std_logic;
    index : in  std_logic_vector(0 downto 0)
      );
    END COMPONENT;



BEGIN

   bla: test
  PORT MAP (
  clk => clk,
  index  => index,
  output => output
  );


   clk_process :process(clk, index, output)
   begin


  clk <= not(clk);

  if (rising_edge(clk) and clk = '1') then
  index <= u2slv(slv2u(index)+1);
  end if;

  if  index = 89 and output = '1'then --
  index <= (others => '0');
  output <='0';
  end if;

  if  index = 34 and output = '0'then --
  index <= (others => '0');
  output <='1';
  end if;

clk_o <= output;

end process;



end rtl;





PS: I am working on a Spartan-6 Atlys Board in case this information is 
needed.

Author: Tobias L. (murxwitz)
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Your Toplevel Entity and the component you try to instantiate are both 
named test, so you have to rename one
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
library work;
use work.convert_pack.all;

entity test_top is --line 30
    Port (
   clk_o : out  STD_LOGIC;
   output : inout std_logic;
   clk : inout std_logic;
   index : inout  std_logic_vector(0 downto 0)

   );
end test_top;

architecture rtl of test_top is


    component test
        PORT(
     output  : out std_logic;
     clk : in std_logic;
    index : in  std_logic_vector(0 downto 0)
      );
    END COMPONENT;



BEGIN

   bla: test
  PORT MAP (
  clk => clk,
  index  => index,
  output => output
  );


   clk_process :process(clk, index, output)
   begin


  clk <= not(clk);

  if (rising_edge(clk) and clk = '1') then
  index <= u2slv(slv2u(index)+1);
  end if;

  if  index = 89 and output = '1'then --
  index <= (others => '0');
  output <='0';
  end if;

  if  index = 34 and output = '0'then --
  index <= (others => '0');
  output <='1';
  end if;

clk_o <= output;

end process;

end rtl;

should work (not tested)

PS: don't use the obsolete
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

: Edited by User
Author: Iluvatar (Guest)
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thanks for the hint, i got now this error message:
Line 71: found '0' definitions of operator "=", cannot determine exact 
overloaded matching definition for "="


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.convert_pack.all;

entity test is
    Port (
   clk_o : out  STD_LOGIC;
   output : inout std_logic;
   clk : inout std_logic;
   index : inout  std_logic_vector(0 downto 0)

   );
end test;

architecture rtl of test is


    component ntest
        PORT(
     output  : out std_logic;
     clk : in std_logic;
    index : in  std_logic_vector(0 downto 0)
      );
    END COMPONENT;



BEGIN

   bla: ntest
  PORT MAP (
  clk => clk,
  index  => index,
  output => output
  );


   clk_process :process(clk, index, output)
   begin


  clk <= not(clk);

  if (rising_edge(clk) and clk = '1') then
  index <= u2slv(slv2u(index)+1);
  end if;

  if  index = 89 and output = '1'then --line 71
  index <= (others => '0');
  output <='0';
  end if;

  if  index = 34 and output = '0'then --
  index <= (others => '0');
  output <='1';
  end if;

clk_o <= output;

end process;



end rtl;

Author: Lothar Miller (lkmiller) (Moderator)
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Pls use the VHDL tags (to be found in the "Formatting options" a few 
lines under "Reply Rules — please read before posting")!

Iluvatar wrote:
> thanks for the hint, i got now this error message:
> Line 71:  found '0' definitions of operator "=", cannot determine exact
> overloaded matching definition for "="
  if index = 89 and output = '1' then 
VHDL has a very strict data type handling. You cannot compare a vector 
with an integer. Those two are COMPLETELY different. And therefore the 
operator '=' don't "know" hao to handle those two operands.
Two solutions:
1. You must compare the same data types
2. you must overload the '=' funktion (yes, its only a function in VHDL)

This here is a stupid lazy "trick":
output : inout std_logic;
clk : inout std_logic;
index : inout std_logic_vector(0 downto 0)
Every beginner thinks to be neat defining ports as inout to read them 
"back". But this is the most easy way to dig holes in the structure of a 
VHDL description. Beeing your boss or your teacher I would degrade you 
for that...  :-o

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