Hi, I'm trying to get an ADT7310 temperature sensor to work (Datasheet: http://www.analog.com/static/imported-files/data_sheets/ADT7310.pdf). However, the chip behaves strangely when I want to read/write register values using SPI. The attached pictures show the signals of a write and subsequent read of the configuration register (addr 0x01). As you can see, the value read from the register does not equal the one written to it (but is always the same). Other values and registers show the same behaviour, and reading registers without first writing to them does not produce the default values specified in the datasheet. I checked all the timing constraints specified in the datasheet and am well within limits (e.g. 400ns CLK high pulse width in the images), but even longer times don't affect this behaviour. I already read that you have to do a reset (send 32 '1's) before using the sensor, and I'm doing that. Is there anything else I'm missing? Regards, Mirko
Attached files:
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write_reg_cfg.png
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read_reg_cfg.png
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Mirko wrote: > I already read that you have to do a reset (send 32 '1's) before using > the sensor, and I'm doing that. Is there anything else I'm missing? Yep. Try changing SPI-Mode.
marc vesely wrote: > Yep. Try changing SPI-Mode. I'm using SPI mode 3 (CPOL=1, CPHA=1) which is correct if I read the datasheet right (the chip clocks data into its registers at the positive edge of CLK). The signals generated also conform to the examples in the datasheet (p. 19f). I also tried all other SPI modes, but none of them produce correct results.
Mirko wrote: > I'm using SPI mode 3 (CPOL=1, CPHA=1) which is correct if I read the > datasheet right (the chip clocks data into its registers at the positive If i read your pictures correct, it seems to be: Idle = LOW Clock_In = on falling edge.
marc vesely wrote: > Idle = LOW > Clock_In = on falling edge. Sorry, could you clarify? Which signal is low on idle? All signals look HIGH to me when I'm not doing anything On the falling edge of SCLK the master (me) sets MOSI to the desired level so the slave (sensor) can read it on the subsequent rising edge, no?
Mirko wrote: > Sorry, could you clarify? Which signal is low on idle? All signals look > HIGH to me when I'm not doing anything Now I'm not sure that I was right. I thought that CLK was reversed and since the master is doing all the job, it could be that the slave reads falling edge as leading edge. The only thing that makes sense is, that you are getting back the register adress previously sent, with reversed edge reading. > On the falling edge of SCLK the master (me) sets MOSI to the desired > level so the slave (sensor) can read it on the subsequent rising edge, > no? Looked into Datasheet - you are doing everything right...
marc vesely wrote: > Looked into Datasheet - you are doing everything right... The only other thing... >The ADT7310 can be operated with CS used as a frame synchronization >signal. This scheme is useful for DSP interfaces. In this case, the >first bit (MSB) is effectively clocked out by CS because CS normally >occurs after the falling edge of SCLK in You are doing that other way around, I believe You are clocking HIGH as bit 7 and Datasheet says: > Bit C7 of the command byte must be set to 0 to successfully begin a > bus transaction. The SPI interface does not work correctly if a 1 > is written into this bit.
So if I understand this right, pulling SS low might cause current MOSI to be read by the ADT7310 as bit c7? When I read that the first time I thought it only applied if SCLK is LOW (i.e. if SS becomes active after the first falling clock edgde) but now I'n not so sure about that anymore. I'll definitely try out pulling SS low after the first falling SCLK edge (or just keeping SS low, that might work..). Sadly I can't test it until tomorrow, but I'll report back then.
Mirko wrote: > I'll definitely try out pulling SS low after the first falling SCLK edge > (or just keeping SS low, that might work..). Sadly I can't test it until > tomorrow, but I'll report back then. Keep it low all the time, send RESET first.
Both keeping SS low the whole time and pulling SS low after the first falling edge of SCLK still produce the same problem for me.
Seems that sometimes a "high" is read as a "low" by the sensor. Do both sides on the SPI bus use the same supply voltage? E.g. using 3.3V on uC side and 5V on sensor side could cause to such an issue, because for the sensor a "high" is specified with 0.7xVDD (=0.7 x 5V = 3.5V).
Both the sensor and the uC (atmega644) are connected to the same power supply (5V). By the way, thanks to you for all the help I've been getting here already.
Mirko wrote: > Both keeping SS low the whole time and pulling SS low after the first > falling edge of SCLK still produce the same problem for me. And tried all other SPI modes again ?
Easylife wrote: > Sensor supply pin is properly decoupled by 100nF? Yes, although it seems to make no difference. marc vesely wrote: > Mirko wrote: >> Both keeping SS low the whole time and pulling SS low after the first >> falling edge of SCLK still produce the same problem for me. > > And tried all other SPI modes again ? Keeping SS low and using SPI Mode 0 (CPOL=0, CPHA=0) seeems to work! I'm not sure where I went wrong reading the datasheet or the diagrams in there, I was pretty sure it had to be Mode 3. But I'm glad it works now. Thanks a lot!
Mirko wrote: > Keeping SS low and using SPI Mode 0 (CPOL=0, CPHA=0) seeems to work! > I'm not sure where I went wrong reading the datasheet or the diagrams in > there, I was pretty sure it had to be Mode 3. Such things are really annoying. Datasheet clearly shows SPI Mode 3. Would be worth contacting Analog Devices regarding this mismatch of datasheet and reality.
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