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Forum: FPGA, VHDL & Verilog Rectangular waveform generator in the range from 0 to 10MHz.


Author: Marek (Guest)
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To pass the subject had to do such a project: Rectangular waveform 
generator in the range from 0 to 10MHz. I have a all code, Behavioral 
simulation is good but post-fit is bed, becouse over time, an indefinite 
condition  'X' on a output.
What is wrong with this code? Please help

My code:
------------------------------------------------------------------------ 
----------
-- Company:
-- Engineer:
--
-- Create Date:    17:25:15 06/14/2014
-- Design Name:
-- Module Name:    Generator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
------------------------------------------------------------------------ 
----------
LIBRARY ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.all;
--use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;



ENTITY Generator IS
PORT  (
      clk       : IN STD_LOGIC;      --100Mhz  (10ns)
    zadajnik1 : IN STD_LOGIC_VECTOR(3 downto 0);
    zadajnik2 : IN STD_LOGIC_VECTOR(3 downto 0);
    zadajnik3 : IN STD_LOGIC_VECTOR(3 downto 0);
    zadajnik4 : IN STD_LOGIC_VECTOR(3 downto 0);
    led1 : OUT STD_LOGIC;
    led2 : OUT STD_LOGIC;
      wyjscie   : OUT STD_LOGIC
    );

END Generator;

ARCHITECTURE Behavioral OF Generator IS

subtype shortint is integer range 0 to 1000000000;
subtype microint is integer range 0 to 9;

    signal nastaw1 : microint;
    signal nastaw2 : shortint;
    signal nastaw3 : microint;
    signal nastaw4 : shortint;

BEGIN

process (clk,zadajnik1,zadajnik2,zadajnik3,zadajnik4)

    variable count : std_logic_vector(29 downto 0) := (others => '0');
    variable count2 : std_logic_vector(29 downto 0) := (others => '0');
    variable count3 : std_logic_vector(3 downto 0) := (others => '0');
    variable count4 : std_logic_vector(3 downto 0) := (others => '0');

    begin

  if rising_edge(clk) then

  nastaw1 <= to_integer(unsigned(zadajnik1));
  nastaw3 <= to_integer(unsigned(zadajnik3));


      if (count = nastaw4) then
        count3 := count3 + 1;
        count := (others => '0');
        if (count3 <= nastaw3) then
          wyjscie <= '1';
        else
          wyjscie <= '0';
        end if;
      end if;
      if (count2 = nastaw2) then
        count4 := count4 + 1;
        count2 := (others => '0');
        if (count4 = nastaw1) then
          count3 := (others => '0');
          count4 := (others => '0');
        end if;
      end if;
      count := count + 1;
      count2 := count2 + 1;
  end if;


----------------------------------------------


if (nastaw2 > nastaw4) then
  led1 <= '0';
elsif (nastaw2 < nastaw4) then
  led1 <= '1';
elsif (nastaw2 = nastaw4) then
  if (nastaw1 > nastaw3) then
    led1 <= '0';
  else
    led1 <= '1';
  end if;
end if;


if ((nastaw1 = 0) or (nastaw3 = 0)) then
led2 <= '1';
else
led2 <= '0';
end if;



end process;



      with zadajnik2 select nastaw2 <=
              1 when "0000",
              10 when "0001", --10
              100 when "0010", --100
              1000 when "0011", --1 000
               10000 when "0100", --10 000
              100000 when "0101", --100 000
              1000000 when "0110", --1 000 000
              10000000 when "0111", --10 000 000
              100000000 when "1000", --100 000 000
              1000000000 when "1001", --1 000 000 000
              10 when others;


      with zadajnik4 select nastaw4 <=
              1 when "0000",
              10 when "0001", --10
              100 when "0010", --100
              1000 when "0011", --1 000
               10000 when "0100", --10 000
              100000 when "0101", --100 000
              1000000 when "0110", --1 000 000
              10000000 when "0111", --10 000 000
              100000000 when "1000", --100 000 000
              1000000000 when "1001", --1 000 000 000
              10 when others;

end Behavioral;

Author: Hans (Guest)
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Marek wrote:
> I have a all code, Behavioral
> simulation is good
Fine. So it shold work on your FPGA too.

> but post-fit is bed, becouse over time, an indefinite
> condition  'X' on a output.
There is an effect, called 'X'-propagation. You can search the reason 
for the 'X'.
Normaly a beahvioral simulation is enough. Post-fit timinig simulation 
is today only used in dodgy designs.
The statical timing analysis with proper clock constraint will help even 
more than a timing simulation.

> What is wrong with this code?
I would change some parts:

Marek wrote:
> LIBRARY ieee;
> use ieee.std_logic_1164.all;
> --use IEEE.STD_LOGIC_ARITH.all;
> --use ieee.std_logic_signed.all;
> use ieee.std_logic_unsigned.all;
> use ieee.numeric_std.all;
1. To make calculation use only numeric_std. Forget 
std_logic_unsigned, std_logic_signed and std_logic_arith. They are 
vendor specific and unstandardised (and wrong compiled to library ieee).


> variable count : std_logic_vector(29 downto 0) := (others => '0');
>     variable count2 : std_logic_vector(29 downto 0) := (others => '0');
>     variable count3 : std_logic_vector(3 downto 0) := (others => '0');
>     variable count4 : std_logic_vector(3 downto 0) := (others => '0');
2. As beginner avoid variables. Learn the specific behaviour of signals 
(latency), after that you can use variables.

3. Use the type unsigned for counters. std_logic_vectors are just a pile 
of bits. To make calculations (like the addition of 1) use unsigned. 
unsigned can easy compared with integer and can easy converted to slv, 
if needed.

regards,
Hans

Author: inzynier polski (Guest)
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Marek wrote:
> with zadajnik4 select nastaw4 <=
osobliwie sformulowanie :-)

Why do you transform the inpus to deicmal?
You should use binary increasing Counters to directly compare to the 
Input Parameters.

- dziwny zadanie ...

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