Forum: FPGA, VHDL & Verilog vhdl test bench

Author: Rockyy Sharma (rockyy)
Posted on:
Attached files:

Rate this post
0 useful
not useful
 library IEEE;

entity test1 is
    Port ( clk : in  STD_LOGIC;
           input1 : in  STD_LOGIC;
           input2 : in  STD_LOGIC;
           output : out  STD_LOGIC);
end test1;

architecture Behavioral of test1 is
      if (clk'event and clk='1') then
        output <= input1 and input2;
        end if;
end process;

end Behavioral;

For the above Program I have created a VHDL test bench like below
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
END test;
ARCHITECTURE behavior OF test IS 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT test1
         clk : IN  std_logic;
         input1 : IN  std_logic;
         input2 : IN  std_logic;
         output : OUT  std_logic

   signal clk : std_logic := '0';
   signal input1 : std_logic := '0';
   signal input2 : std_logic := '0';

   signal output : std_logic;

   -- Clock period definitions
   constant clk_period : time := 1 ns;
    -- Instantiate the Unit Under Test (UUT)
   uut: test1 PORT MAP (
          clk => clk,
          input1 => input1,
          input2 => input2,
          output => output

   -- Clock process definitions
   clk_process :process
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
      -- hold reset state for 100 ns.
      wait for 10 ns;     
        input1 <= '0';
        input2 <= '0';
        wait for 20 ns;
        input1 <= '0';
        input2 <= '1';
        wait for 30 ns;
        input1 <= '1';
        input2 <= '0';
        wait for 40 ns;
        input1 <= '1';
        input2 <= '1';

   end process;


but after simulating the behavioural Model i am getting the value of
clk = U
input1 = U
input2 = U
output = U

I am very new to VHDL,Can any one let me know why I am getting U as 
value and not getting the Signal.Check the attach file for the output.

Author: Bitflüsterer (Guest)
Posted on:

Rate this post
1 useful
not useful
Declare your testbench, i.e. entity "test" as top level. Not "test1", 
which is the DUT (device under test) itself.
Another possibility is, that you marked the test1 entity when starting 
the simulator. Mark the testbench test instead, when starting 

Author: Rockyy Sharma (rockyy)
Posted on:

Rate this post
0 useful
not useful
Thanks for the information its working


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.