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Forum: FPGA, VHDL & Verilog multiple connection


Author: sebgimi (Guest)
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Hi,

I want to connect 2 components in vhdl but I have some trouble to write 
the code because of multiple connections in port map.

The output of the component is a real_vector(0 to 3) and is connected to 
multiple outputs of an other component as below:

fast_anlog_in(0) => adc1_vinp(0), adc2_vinp(0)
fast_anlog_in(1) => adc1_vinn(0), adc1_vinp(1), adc2_vinn(0), 
adc2_vinp(1)
fast_anlog_in(2) => adc3_vinp(0)
fast_anlog_in(3) => adc3_vinn(0), adc3_vinp(1)

What is the good way to proceed ?

Thank you !

Author: Lothar Miller (lkmiller) (Moderator)
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sebgimi wrote:
> The output of the component is a real_vector(0 to 3) and is connected to
> multiple outputs of an other component as below:
You cannot connect multiple outputs unless your data type can resolve 
such conflicts.
If you have to connect several outputs to one input you must use a 
multiplexer to select the active output.

Author: sebgimi (Guest)
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Lothar Miller wrote:
> If you have to connect several outputs to one input you must use a
> multiplexer to select the active output.

I also thought about a multiplexer but in my case the two outputs can be 
active in the same time...

FYI: signals are real type

Thank you

Author: Lothar Miller (lkmiller) (Moderator)
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sebgimi wrote:
> but in my case the two outputs can be active in the same time
And: which one is "valid" for the input? Which one must "win" the input? 
If one output is 1000 and the other is 500, what is the result?

: Edited by Moderator
Author: sebgimi (Guest)
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Sorry, maybe I was not clear enough...

I have one component with one output that I want to connect to several 
outputs of an other component. In attchment you have a draw of the 
system for a better understanding.

Author: Duke Scarring (Guest)
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sebgimi wrote:
> that I want to connect to several
> outputs of an other component
I connect one output to the next input.
Sometimes I connect one output to several inputs.
But I do never ever connect multiple outputs together (except for I2C 
connections).

Duke

Author: greg (Guest)
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sebgimi wrote:
> I have one component with one output that I want to connect to several
> outputs of an other component. In attchment you have a draw of the
> system for a better understanding.

I guess that's a typo and you actually want to connect a single output 
to multiple inputs? Everything else won't make sense.

Author: Schlumpf (Guest)
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The structure on the photo is not the structure typically described via 
port map.
It is a component that is instantiated within another component.
So give the signal a name und "attach" the outputs from the "inner" 
component to the signal

sig1 <= Out1

and then attach the outputs of the "outer" component to that signal

Output1 <= sig1;
Output2 <= sig1;

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