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Forum: FPGA, VHDL & Verilog counter as function


Author: itay (Guest)
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we have state machine in the main function that has a clock . in the 
transition between two states we need to wait for a period of time (the 
time  varies from time to time and we need to calculate it seperatly) 
and then to move to the next state.
In order to implement this we want to use a counter as a function. but 
we can't use process (CLK) in a function. what can we do else?

Author: Lothar Miller (lkmiller) (Moderator)
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itay wrote:
> In order to implement this we want to use a counter as a function. but
> we can't use process (CLK) in a function.
I want to celebrate Christmas in summer! But summer is in July and 
Christmas in December.

> what can we do else?
I will have to celebrate Christmas in winter. And you will have to use a 
process for the counter...

Or the other way: because you obviously don't know what a function in 
VHDL is and what a functions capabilites are you should not use it at 
all.

A function in VHDL is much different from a function in C or BASIC.

: Edited by Moderator

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