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Forum: FPGA, VHDL & Verilog please help edge detection


Author: Mark Jomari (imaroj)
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why this is happening?? please,. i just used 2Mpixel camera then used 
the vga as the output. thank you for your response
.,

Author: Lothar Miller (lkmiller) (Moderator)
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Mark Jomari wrote:
> why this is happening?
What happens and what did you expect instead?
What way do you get from one to the other?

Read your own post as everybody here must read it: without ANY knowledge 
about your problem. You will see: nobody cannot understand anything!


And: what has your problem to do with FPGAs, Asics or other programmable 
logic?
If so: what platform? What hardware? What toolchain?

: Edited by Moderator
Author: Mark Jomari (imaroj)
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im sorry,. what i mean is,. on the left side is the sobel edge 
detection, and on the right side is the grayscale input,,
,. why the output looks like that?

: Edited by User
Author: Bitflüsterer (Guest)
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Mark Jomari wrote:
> im sorry,. what i mean is,. on the left side is the sobel edge
> detection, and on the right side is the grayscale input,,
> ,. why the output looks like that?

The output looks like it looks, because you applied what you applied. 
:-)


Once again. Read your question and consider what a reader must know in 
order to help you.

So, what do you expect and in which specific does it deviate from what 
you get?

Author: Hans Ulli Kroll (elektroman)
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Hmmm,

you have a "shadow"

wrong double/buffering ??

or you have only one buffer for input and output.
This is wrong.

Author: Mark Jomari (imaroj)
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i think so,. because in my simulation in modelsim, the result of the 
sobel edge detection takes 7 posedge clk before getting the magnitude,, 
how can i control the delay of the output of vga,?

Author: FPGA advisor (Guest)
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that cannot be the reason for these double image one can see in your 
examples. this is either a sobel filter issue or something else.

Author: Mark Jomari (imaroj)
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i use pipelining in this program,, as of now, it is working correctly,, 
one question,, hows the clken works?

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