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Forum: FPGA, VHDL & Verilog adc-fpga interface guidelines for vhdl


Author: jeorges FrenchRivera (Company: xlue) (khal1985)
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Hi,

I want to interface 4 separate ADCs or (One ADC that can handle 4 
different inputs in the same time) with Cyclone IV fpga. The fpga 
masters the control lines of the ADCs/ADC and it also acquires the 
digital data from the ADCs/ADC through parallel or serial bus(not 
decided yet).

I will have to acquire data from all four Adcs/ADC simultaneously. I am 
a beginner when it comes to VHDL and I have no idea on the time span of 
the data acquisition.

Do you have some references about chips that i can use for this stuff?

What are the things I will have to consider in VHDL to make sure that 
all 4 Adcs are controlled effectively and data is acquired without any 
time lag between one another.

Replies in terms of Logic blocks in the code and example code for ADC 
data acquisition will be really helpful.

Best Regards

Author: St. D. (st_d)
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Decide on your ADC and try to realize the communication interface, which 
is described within the datasheet, via VHDL. If you are a total 
beginner, start with simpler stuff, for ex. design a UART module.
As you gain a bit experience with FPGA design, you will see that your 
current question makes very little sense ;)

Author: St. D. (st_d)
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opencores.org will be also a good friend to you...

Author: Achim S. (Guest)
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jeorges FrenchRivera wrote:
> I will have to acquire data from all four Adcs/ADC simultaneously.

There are multichannel ADCs which sample the input voltage on all 
channels simultaneously (AD7606 for example). The data transfer to FPGA 
happens sequentially afterwards, but the voltage on all channels ist 
measured at the same point in time.

From VHDL point of view the control of the AD7606 just needs an 
SPI-block. But you have to ensure, that the ADC also fullfills your 
other requirements (which you did not describe), like samplerate, analog 
bandwidth, accuracy, ....

Author: Librarian (Guest)
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jeorges FrenchRivera wrote:
> Replies in terms of Logic blocks in the code and example code for ADC
> data acquisition will be really helpful.

http://www.ti.com/lit/ug/slaa545/slaa545.pdf

Best regards,

Author: jeorges FrenchRivera (Company: xlue) (khal1985)
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Ok, thank you all for your replies. i take notes.

@  Achim S:
>But you have to ensure, that the ADC also fulfills your
other requirements (which you did not describe), like sample rate, 
analog
bandwidth, accuracy

I need a sample rate of 100 kSPS for ecah channel minimum.analog
bandwidth ±5 V, accuracy 16 bits

Best regards

Author: Achim S. (Guest)
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jeorges FrenchRivera wrote:
> I need a sample rate of 100 kSPS for ecah channel minimum.analog
> bandwidth ±5 V, accuracy 16 bits

Then the AD7606 might indeed be a good solution for you. It delivers up 
to 200kS/s (simultaneous on all channels), input range can be configured 
to +/-5V, resolution is 16 Bit.

Some of your specifications don't get to the point (mixing bandwidth 
with input range and -most probably- mixing accuracy with resolution).
But the AD7606 really looks like a good starting point. You should have 
a closer look at it and see, if it really meets all your requirements.

Author: jeorges FrenchRivera (Company: xlue) (khal1985)
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Ok, thank all you for answers, i'll take your remarks in consideration

Best regards

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