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Forum: FPGA, VHDL & Verilog assign generic value to an output vhdl


Author: guy (Guest)
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Hi everyone,

I'm a newbie in vhdl and I would like to know if is it possible to 
assign a generic value to an output in vhdl.

For instance:
entity xxx is

    generic(value : real);

    port (a : in real;
          b : in real;
          s : out real);

end xxx;

archi archi of xxx is
begin

      s <= value;

end archi;

If it is not can you help me to find an other way please ?

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
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guy wrote:
> I would like to know if is it possible to assign a generic value to an
> output in vhdl.
It is.

> If it is not can you help me to find an other way please ?
A way to where?

: Edited by Moderator
Author: guy (Guest)
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Ahah, what is the way to do what I want? I tried as I have wrote it 
above but in simulation I have not the good value.

Author: Bitflüsterer (Guest)
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guy wrote:
> Ahah, what is the way to do what I want? I tried as I have wrote it
> above but in simulation I have not the good value.

As Lothar already wrote: Your code is sufficient to do what you want. If 
there is still a problem, please show the context (i.e. the testbench) 
and tell us in detail how and by what means you came to the conclusion, 
that the result is not what you expect.

Author: guy (Guest)
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You're right, my code was good indeed. I don't know why I had wrong 
values earlier. It is ok now. Thank you

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