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Forum: FPGA, VHDL & Verilog open input vhdl


Author: bob (Guest)
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Hi all,

In a process I want to do a thing like that:

if D = open then

      S <= 'Z';

end if;

But D = open is not understood by the compiler. Do you know an other 
way?

Thank you

Author: VHDL (Guest)
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How are you planning to sense the open case? An input can be '1' (high) 
or '0' (low); if you want to sense the unconnected case, you need a 
pull-up or pull-down resistor then!

Author: Bitflüsterer (Guest)
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You unfortunately didn't mention, what your intent is. However, the 
standard libraries do not contain a type which has 'open' as one of its 
values. The only context in which the keyword is defined is the 
connection (instantiation) of an entity to signals, where a port defined 
by an entity may be left open in caes where its input is not needed (and 
a default value is assigned).

So the question is: Did you define a type which contains 'open' as a 
value? (I think this would not be possible, but I never tried, so I am 
carefully not deny such a possibility). In case you didn't, how, do you 
think, may the circuitry determine whether a port is physically 
unconnected (floating)? And in case you considered that allready (and 
correctly), you must be advised to use a generic to indicate that a 
certain port is unconnected in your special case (instantion) and may 
check for that generic.

Author: bob (Guest)
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Sorry for the lack of explaination!

I have to describe a CAN transceiver, in the doc 
(http://www.ti.com/lit/ds/symlink/sn65hvd230.pdf) there is a truth table 
with a case of an open input which gives a high impedance output.

So my point is to describe this case in vhdl.

Author: Bitflüsterer (Guest)
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But that's still insufficient. I can't exaggerate the necessity of 
precise and clear desriptions in technology.

The term "to describe a CAN transceiver" is ambiguous in context of 
FPGAs.
Do you want to emulate that transceiver by means of an FPGA or do you 
want to interface that IC to an FPGA? Your question implies that the 
former is the case (but I'ma addicted to precise statements).

However, you can't determine (more exactly: describe a synthesizable 
structure which determines) whether an input of an FPGA is connected to 
an external signal which in turn is in High-Z state or not. All you can 
do is, to set an output of a FPGA to High-Z (or use it [please note that 
I speak about High-Z not open] non-synthesizable in a condition).

Please tell us more detail. Every detail you have.

Author: Bitflüsterer (Guest)
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I must add that your statement "to describe that a CAN transceiver" is 
in fact not imprecise but it is highly unlikely. Sorry. I may be allowed 
to doubt it but not to deny it in regard to precision.

Author: bob (Guest)
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Sorry again,

My work is just about simulation in VHDL, not to synthesize my code on a 
FPGA.
So maybe I can use the U value of std_logic type for the case of an open 
wire ?

Author: Bitflüsterer (Guest)
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Uh. oh, the third case. :-)  (I told you to be precise ;-) )

I think 'U' should do. 'High-Z' should do too. But for Simulation only. 
(Please check the docs for the exact spelling of the HIGH-Z-value).

Author: Bitflüsterer (Guest)
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It's 'Z'. You already wrote it.

Good luck.

Author: bob (Guest)
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Thank you!

Author: Bitflüsterer (Guest)
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A pleasure.

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