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Forum: FPGA, VHDL & Verilog delay not wanted vhdl


Author: angelo (Guest)
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Hi every one,

I'm writing a code for a dac in vhdl and I have some troubles during 
simulation: a delay appears on two signals what is not what I want...

My code:
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity dac is

  generic (data_width : integer;
     SDI_width  : integer;
     REF        : real);
     
  port(  SDI   : in  std_logic_vector (SDI_width - 1 downto 0);
    SDO   : out std_logic_vector(SDI_width - 1 downto 0);
    SCK   : in  std_logic;
    CLR   : in  std_logic;  -- low level active
    CS_LD : in  std_logic;   -- '0': CS / '1': LD
    LDAC  : in  std_logic;  -- low level active
    Vout  : out real
      );
    
end dac;

architecture archi of dac is  

signal data      : std_logic_vector(11 downto 0);
signal data_real : real;

begin

  data <= SDI(15) & SDI(14) & SDI(13) & SDI(12) & SDI(11) & SDI(10) &
    SDI(9) & SDI(8) & SDI(7) & SDI(6) & SDI(5) & SDI(4);    
  
  P1: process(SCK)
  begin
    
    data_real <= (real(to_integer(signed(data))));

    if (CLR = '0' or CS_LD = '0') then
    
      Vout <= 0.0;
      
    elsif (SCK'event and SCK = '1') then
      
      Vout <= data_real/(2.0**data_width) * REF;
      
    end if;
    
  end process;
  
      
end archi;

In simulation this is a delay of 5 ns on the "data_real" signal and 15 
ns on the signal "Vout".

Do you know what is wrong in my code and how to fix it please ?

Author: Lothar Miller (lkmiller) (Moderator)
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angelo wrote:
> In simulation this is a delay of 5 ns on the "data_real" signal and 15
> ns on the signal "Vout".
Your problem ist the wrong sensitivity list...

Try this and think about it:
  P1: process(SCK,data,CLR,CS_LD) ...

THis line can be shortened:
data <= SDI(15) & SDI(14) & SDI(13) & SDI(12) & SDI(11) & SDI(10) &
    SDI(9) & SDI(8) & SDI(7) & SDI(6) & SDI(5) & SDI(4);
Try it this way:
data <= SDI(15 downto 4);

: Edited by Moderator
Author: angelo (Guest)
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Hi,

Thank you for your answer, with all your advices the issue is 
fixed...partially.

No more delay on data_real signal, but still on Vout signal. Now it's a 
5 ns delay instead 15 ns.

Did I miss something ?

Author: angelo (Guest)
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Never mind, I'm just silly!

It's all good! Cheers

Author: Lothar Miller (lkmiller) (Moderator)
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angelo wrote:
> It's all good!
To all the others: there must be a "delay" due to the clock, obviously.

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