People say there's a PCIe Endpoint "Hard Core" inside the Virtex 7 FPGA. But, from what I see in some documents, there's Hard IP in a flash outside of the FPGA, which is load via a CPLD to the FPGA. Xilinx calls this Tandem Method, Altera calls it CvP. And if the ASIC in side the FPGA exits in Virtex 7, why do we need the Tandem Method?
The "hardware" for PCIe is present in the FPGA, but nevertheless it needs to be configured after startup to run properly (like pretty much everything in the FPGA). This configuration data is read from the external Flash. The configuration takes some time, and that delay might be too long in a PCIe system. It might happen, that due to the configuration-delay the PCIe device gets not properly recognized in the system. The special thing about the "tandem method" is, that first a small part of the configuration is loaded quite fast (so that the PCIe device is functional in time). The long lasting configuration of the complete FPGA is then done in a second step (either from Flash, or over the PCIe-Link).
Thank you. So I guess Xilinx calls the 'hardware' the 'Integrated Block', and the integrated block IS an ASIC inside FPGA. Again, thanks.
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