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Forum: FPGA, VHDL & Verilog using generate with clk


Author: stas (Guest)
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Hi,

I'm using generate to create 32 dff's to work as a shift register,
that part works great.
The problem is, that i want to input data only on rising edge of the 
clock,
but the actual insert takes place half clk after that.
Do i need to change the generate itself?

thx !

this is the component that activates the generate:
begin 
 
  dffx: for i in 1 to 31 generate
  
  lsb: if i=1 generate 
    dff1: dff24 port map
    (clk,rst,data_in,fir_array((24*i-1) downto (i-1)*24));
  end generate lsb;
   
   msb: if (i>1)and(i<=31) generate 
    dffs: dff24 port map
    (clk,rst,fir_array((24*(i-1)-1) downto (i-2)*24),fir_array((24*i-1) downto (i-1)*24));
  end generate msb;
    end process;
  end generate dffx;
this is the component that the generate use:
architecture beh of dff24 is


  begin
  
    process (clk, rst)    
      
      begin
        if(rst = '0') then
          q <= "000000000000000000000000" ;
      
        else if (rising_edge(clk)) then
           q <= d;
         end if;
        end if;
      end process;
      
  end beh;

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
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Try that for posting VHDL code:
[vhdl]
  VHDL code
[/vhdl]

stas wrote:
> The problem is, that i want to input data only on rising edge of the
> clock, but the actual insert takes place half clk after that.
Which insert to what?

stas wrote:
> I'm using generate to create 32 dff's to work as a shift register,
You are using 24*32 dffs for a amazing complex looking shift register...
What do you want to get with that? What is your actual task to do?

Author: stas (Guest)
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 this is the component that activates the generate:
begin 
 
  dffx: for i in 1 to 31 generate
  
  lsb: if i=1 generate 
    dff1: dff24 port map
    (clk,rst,data_in,fir_array((24*i-1) downto (i-1)*24));
  end generate lsb;
   
   msb: if (i>1)and(i<=31) generate 
    dffs: dff24 port map
    (clk,rst,fir_array((24*(i-1)-1) downto (i-2)*24),fir_array((24*i-1) downto (i-1)*24));
  end generate msb;
    end process;
  end generate dffx;


this is the component that the generate use:
architecture beh of dff24 is


  begin
  
    process (clk, rst)    
      
      begin
        if(rst = '0') then
          q <= "000000000000000000000000" ;
      
        else if (rising_edge(clk)) then
           q <= d;
         end if;
        end if;
      end process;
      
  end beh;


the project itself is to build fir filter, this part of the project 
should only store every sample (every sample size is 24 bits and there 
are 32 samples), every rising edge i wish to insert the new sample to 
the first flipflop and move the last sample to the next.
The result would be 32 samples in 32 flipflops as the last one in is in 
the number 1 flip flop.

Author: Achim S. (Guest)
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So you want to store 32 samples in 32 registers, where each registers 
contains 24 Flipflops, correct?

stas wrote:
> but the actual insert takes place half clk after that.

How do you come to this conclusion? Observed by oscilloscope? Observed 
by behavioral simulation or timing simulation?

Everthing in the shown code works on the rising clk edge. So in 
behavioral simulation you should see the FFs are switching triggered by 
the rising clk edge.

But if you run timing simulation or monitor the FPGAs outputs with an 
osci, you will see the switching after some delay (cause the switching 
takes some time, the routing from the FF to the output causes some 
delay, ...). This delay might look like the switching happens at the 
falling clk edge.

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