EmbDev.net

Forum: FPGA, VHDL & Verilog Basic ALU in VHDL


Author: VHDL_Help (Guest)
Posted on:

Rate this post
0 useful
not useful
Hi, first time posting! I'm trying to create a basic ALU. However, when 
I try to synthesize, I get the following errors:

ERROR:Xst:2588 - Port <a> of top entity <ALU> is not constrainted.
ERROR:Xst:2588 - Port <b> of top entity <ALU> is not constrainted.
ERROR:Xst:2588 - Port <op> of top entity <ALU> is not constrainted.
ERROR:Xst:2588 - Port <y> of top entity <ALU> is not constrainted.

Any help please?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ALU is
    Port ( a : in  STD_LOGIC_VECTOR;
           b : in  STD_LOGIC_VECTOR;
           c_in : in  STD_LOGIC;
           op : in  STD_LOGIC_VECTOR;
           y : out  STD_LOGIC_VECTOR;
           c_out : out  STD_LOGIC;
           v : out  STD_LOGIC;
           z : out  STD_LOGIC;
           s : out  STD_LOGIC );
end ALU;

architecture Behavioral of ALU is
  signal signal_a : STD_LOGIC_VECTOR (7 downto 0);
  signal signal_b : STD_LOGIC_VECTOR (7 downto 0);
  signal signal_c_in :STD_LOGIC;
  signal signal_output : STD_LOGIC_VECTOR (7 downto 0);
  signal signal_c_out : STD_LOGIC;
  
  signal unsigned_a, unsigned_b : unsigned (7 downto 0);
  signal unsigned_c_in : unsigned (0 downto 0);
  signal unsigned_output : unsigned (8 downto 0);
  
  signal not_a : STD_LOGIC_VECTOR (7 downto 0);
  signal a_and_b : STD_LOGIC_VECTOR (7 downto 0);
  signal a_or_b : STD_LOGIC_VECTOR (7 downto 0);
  signal a_xor_b : STD_LOGIC_VECTOR (7 downto 0);
  
  signal signal_y : STD_LOGIC_VECTOR (7 downto 0);

begin
  signal_a <= NOT(a) when op = "0110"
          else a;
  
  signal_b <= NOT(b) when op = "1111"
          else "11111111" when op = "1110"
          else "00000000" when op = "0111" OR op = "0001"
          else b;
  
  signal_c_in <= '1' when op = "1111" OR op = "0001" OR op = "0110"
            else '0' when op = "1000"
            else c_in;
  
  not_a <= NOT(a);
  
  a_or_b <= a OR b;
  
  a_and_b <= a AND b;
  
  a_xor_b <= a XOR b;
  
  signal_y <= signal_output when op = "0000" else -- ADD
          signal_output when op = "1111" else -- SUB
          signal_output when op = "0110" else -- NEG
          signal_output when op = "0001" else -- INC
          signal_output when op = "1110" else -- DEC
          
          not_a when op = "0101" else
          a_or_b when op = "0111" else
          a_and_b when op = "0110" else
          a_xor_b when op = "1000" else
          "--------";
    
  
  unsigned_a <= unsigned(signal_a);
  unsigned_b <= unsigned(signal_b);
  unsigned_c_in(0) <= signal_c_in;
  

  unsigned_output <= ("0" & unsigned_a) + unsigned_b + unsigned_c_in;
  signal_output <= std_logic_vector(unsigned_output(7 downto 0));
  signal_c_out <= unsigned_output(8);
  
  
  y <= signal_y;
    
  
  v <=  ((signal_a(7) AND signal_b(7) AND NOT signal_output(7)) 
      OR (NOT signal_a(7)AND NOT signal_b(7) AND signal_output(7))) 
      when op = "0000" OR op = "1111" OR op = "0110" OR op = "0001" OR op = "1110"
      else '0';
  
  z <=   '1' when signal_y = "00000000"
      else '0';
      
  s <=   signal_y(7);
          
      
  c_out <= signal_c_out when op = "0000" OR op = "1111" OR op = "0110" OR op = "0001" OR op = "1110"
        else '0';

end Behavioral;


Author: Bitflüsterer (Guest)
Posted on:

Rate this post
0 useful
not useful
You forgot to declare the width of the vectors.

BTW: c_out seems to be a vector too.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.