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Forum: FPGA, VHDL & Verilog syncronize asynchrone input


Author: tester (Guest)
Posted on:

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I am trying to synchronize an asynchrone input, to make my code work, 
but it does still not not.. so i was wondering if the way i 
synchronized, and debounched my signal might be incorrect.

This is how i am doing it
Process(clk)
begin
if rising_edge(CLK) then 
  if switch = "0000" then 
    data_out <= "0000";
  else
    data_out <= switch;
  end if;
end if;
end process;  
  

process( Clk )
variable oldbtn:std_logic_vector(3 downto 0):="0000";
variable counter: integer range 0 to 49999999;
begin
  if rising_edge(clk) then 
    if (data_out XOR oldbtn) /= "0000" then 
      counter:= 0;
      oldbtn:=switch;
    else
      counter:=counter + 1;
      if (data_out XOR oldbtn) = "0000"  and counter = 49999999/4999999 then 
        button <= oldbtn;
      end if;  
    end if;
  end if;  
end process;

First process is for syncronizing the signal with the clock, and the 
other one is the debounching.

Are they incorrectly made or aren't they incorrectly made?

Author: Lothar Miller (lkmiller) (Moderator)
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tester wrote:
> but it does still not not..
How did you find that out? What do you expect? And what happens?

Pls attach the whole vhdl-file (with *.vhd or *.vhdl extension), so that 
the libraries and the port definiton also can be seen...

tester wrote:
> First process is for syncronizing the signal with the clock, and the
> other one is the debounching.
> Are they incorrectly made
This is unnecessary because at this position data_out and oldbtn MUST be 
equal:
     if (data_out XOR oldbtn) = "0000"
Think about that...

> Are they incorrectly made
A switch bounces in the milliseconds range. You are syncing way, way 
faster (in the sub microseconds range). First step is to implement a 
prescaler, so that you are in the correct time division...

> Are they incorrectly made
They are much too complicated. The first process can be written as a 
concurrent description without ANY change in behaviour:
    data_out <= switch when rising_edge(clk);

Why digging around with code like this
    if (data_out XOR oldbtn) /= "0000" then 
when VHDL is able to handle it much better readable this way:
    if (data_out /= oldbtn) then 


BTW:
data_out is a fairly bad name for a sync'ed switch...

Debouncing is only the first step. Next will consequently be a 
edge-detection. Have a look at this (try google translator, its German):
http://www.lothar-miller.de/s9y/categories/5-Entprellung

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