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Forum: FPGA, VHDL & Verilog std_logic_vector won't "keep" certain values


Author: Amir (Guest)
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I was asked to design a simple can dispensing machine using VHDL.
I have an input called CoinIn and is defined as an std_logic_vector(1 
downto 0);
for some reason, when I try to force it with a "11" it will treat it as 
a "01" and when i try to force it with a "10" it will treat it at "00".
Does anyone have any idea what the problem might be?

Author: Amir (Guest)
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Here's the code BTW (it's not 100% ready yet):
library ieee;
use ieee.std_logic_1164.all;

ENTITY FSM IS
PORT (CLK : in std_logic; --Clock, active high
      RSTn : in std_logic; --Async. Reset, active low
      CoinIn : in std_logic_vector (1 downto 0) ; --Which coin was inserted
      Soda : out std_logic := '0'; --Is Soda dispensed ?
      CoinOut : out std_logic_vector (1 downto 0) --Which coin is dispensed?
  );

END ENTITY;

ARCHITECTURE behavior of FSM IS
  TYPE state IS ( start, change, can, pending );
  SIGNAL present_state, next_state : state;
  SIGNAL Count : integer range 0 to 6:=0;

BEGIN
  PROCESS (RSTn, clk, CoinIn) --sync part
  BEGIN
    IF RSTn ='0' THEN
      present_state <= start;
    ELSIF rising_edge(clk) THEN  
      present_state <= next_state;
    END IF;
  END PROCESS;
  
  PROCESS (CoinIn, clk, present_state, next_state) --combinational 
  VARIABLE SodaVar : std_logic;
  VARIABLE CoinOutVar : std_logic_vector(1 downto 0);
  BEGIN
    CoinOutVar := "00";
    CASE present_state is
      WHEN start =>
        SodaVar := '0';
        IF CoinIn = "01" then
          next_state <= pending;
          count <= 1;
        ELSIF CoinIn = "10" then
          next_state <= can;
          count <= 0;
        ELSIF CoinIn = "11" then
          next_state <= change;
          count <= 5;
        ELSIF CoinIn = "00" THEN 
          next_state <= start;
          count <= 0;
        END IF;
      WHEN pending =>
        SodaVar := '0';
        IF CoinIn = "01" then
          next_state <= can;
          count <= 2;
        ELSIF CoinIn = "10" then
          next_state <= change;
          count <= 3;
        ELSIF CoinIn = "11" then
          next_state <= change;
          count <= 6;
        ELSIF CoinIn = "00" then
          next_state <= pending;
        END IF;
      WHEN change =>
        SodaVar := '0';
        IF ((count - 2) = 1) then 
          CoinOutVar := "01";
          count <= 0;
          next_State <= can;
        ELSIF ((count -2) = 0) then
          next_state <= can;
          count <= 0;
          CoinOutVar := "00";
        ELSE          
          next_state <= change;
          count <= count - 2;
          CoinOutVar := "10";
        END IF;
      WHEN can =>
        next_state <= start;
        SodaVar := '1';
        count <= 0;
    END CASE;
    Soda <= SodaVar;
    CoinOut <= CoinOutVar;
  END PROCESS;
END ARCHITECTURE;

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
Posted on:
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Amir wrote:
> Here's the code BTW
Please use the formatting tags (see screenshot).

> when I try to force it with a "11" it will treat it as a "01"
How do you see that?
How do you "force" it?
Don't you have a test bench for this vending machine?

: Edited by Moderator

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