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Forum: FPGA, VHDL & Verilog Cache memory


Author: Mionxsq Lopbc (cmione15)
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How can i write a Cache Memory project in vhdl?? The cache is copy back 
2-way... i'm trying to make a behavior description... but it's not 
working.

Author: Lothar Miller (lkmiller) (Moderator)
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Mionxsq Lopbc wrote:
> but it's not working.
How did you find that out? What do you expect and what do you get?

Just a little hint: VHDL is not C!!!
(I cannot make enough exclamation marks!!)
What you did is a kind of controller that may be working if it is 
executed sequentially on a CPU. But it will never work as you expect on 
hardware with VHDL. Read my comments...
         if (Valid='1') then
            -- forget about functions the first half year of your VHDL career. 
            -- if you don't want to write the mux inline, then have a look for "components" and "component instantiation"
            DataProc<=mux4x1(Cache_OUT(15 downto 0),Cache_OUT(31 downto 16), Cache_OUT(47 downto 32),Cache_OUT(63 downto 48),Palavra); 
            ...
         else   -- to come here Valid must be '0'
             Valid <= validade(V,TAG1,TAG2); -- 
             if (Valid='1') then -- the following code will NEVER be  "reached", 
                                 -- because a SIGNAL in VHDL behaves not the way you want. 
                                 -- Here /Valid/ is '0', because the "new" value of /Valid/ 
                                 -- is updated at the end of the process.
                 ...               

: Edited by Moderator
Author: Mionxsq Lopbc (cmione15)
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I'm trying to do it in a structural description. But I don't know how to 
connect them to make it works.

Author: Lothar Miller (lkmiller) (Moderator)
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Mionxsq Lopbc wrote:
> I'm trying to do it in a structural description.
Pls. attach vhdl files. I cannot open rar files on my tablet...

Author: Mionxsq Lopbc (cmione15)
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