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Forum: FPGA, VHDL & Verilog Verilog LCD1602


Author: JC Ch (jamesearl_c)
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Hi guys, I am a newbie here, I just wanna know if there is something 
wrong with my code, I converted the vhdl code in the attached link to 
verilog and it is not working. I am not sure if I used the correct 
syntax. (btw, i removed the counter and replaced it with just a single 
character A).

http://www.cosmiac.org/pdfs/09Tutorial7.pdf

: Edited by User
Author: Lattice User (Guest)
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This is totally broken.

The orginal VHDL code uses enumrations for its state values, verilog 
doesn't have an equivalent concept.

You have to replace each enumerated state value, with unique constant. 
You can use localparam or `define to assign the values a meaningful 
name.

Author: JC Ch (jamesearl_c)
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So I only have to change the declaration to 'define or localparam? About 
the state machines, is it alright to use the case statement?

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