Forum: FPGA, VHDL & Verilog Problems with getting into state.

Author: State problems (Guest)
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I have a problem with timing in my program.

I have this codepiece
variable prescaler: integer range 0 to 50000000;
Variable control: std_logic_vector(1 downto 0 ):= "00";
variable pointer: integer range 0 to 11:=0;
variable test: std_logic:='0';
variable error: std_logic:='0';
if rising_edge (clk) then 
  if control = "00" and error = '0' then 
    winLEd <= "00";
      if(prescaler < 49999999/1) then   
        prescaler := prescaler + 1;    
        prescaler := 0;
        top_pointer := top_pointer + 1;  -- Top pointer increment
        control := "11";  --- trigger event to get to new state
      end if;
  end if;    
  if control = "11"  and error = '0' then 
    winLEd <= "11";
    Led <= LISTEN(pointer-1);  
      if pointer > (top_pointer) then   -- If pointer is higher than toppointer, it means the sequence has to be incrementet. 
        LED <= "000000";
        control := "00";
        pointer := 0;
        test := '0';
        error:= '0';
      end if;
      if switch = LISTEN(pointer-1) and pointer<= top_pointer then -- Checks if the switch match the sequence. 
        pointer:= pointer +1;
      end if;
      if switch /= LISTEN(pointer-1) and switch /= "0000" then  -- if it doesn not match, error will be set high => trigger an new state. 
        LED(4) <= '1';   
        error:= '1';    
      end if;      
      if switch = "0000" then
        LED(4) <= '0';
        error:= '0';
        control := "11";
      end if;                  
  end if; 
   if error = '1'  and control = "10" then  -- stays here infinetly until board is reset. 
    Led(4) <= '1';
    winLED <=  "10";
  end if; 
end if;              
end process;

I've commented the code to explain how it works.
LIsten is a array which contains different sequences.  The idea is that 
the user have to activate the switch so they match the sequence from the 
My problems is that when i activate the switch for the first sequence, I 
automatically end in the error state,

I think it is because the clock. it is 50 mhz, and therefore the next 
sequence check appear while the switch is down from the first check.

Is there a way i can resolve this problem.
i tried adding a delay but that doesn't help so i am quite lost here..


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