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Forum: FPGA, VHDL & Verilog Why is this incorrect??


Author: John Mayer (215)
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I don't get why this is incorrect???

i am trying to make hierachical design, but i am getting som weird 
errors.
this is my code.
entity top is
    Port ( CLock : in  STD_LOGIC;
           LED : out STD_LOGIC_vector(3 downto 0);
           Switch : in  STD_LOGIC);
end top;
architecture Behavioral of top is
Signal numBER: std_logic_vector (1 downto 0);

component randomnumber 
port (
  clk : in std_logic;
  gameon: in std_logic;
  bitteD: out std_logic_vector (1 downto 0)
      );
end component;
component randtosequence
Port (
  LED1 : out  STD_LOGIC_VECTOR (3 downto 0);
  randbit : in  STD_LOGIC_VECTOR (1 downto 0)
    );
end component;

begin
randomnumber1 : randomnumber port map(clk => Clock, gameon => Switch, bitted => number); 
rantosequence1: randtosequence port map(randbit <= number);
LED <= LED1;
end Behavioral;

I am getting these error which i don't understand.

ERROR:HDLParsers:3312 - "C:/.Xilinx/randomnumber/top.vhd" Line 56. 
Undefined symbol 'randbit'.
ERROR:HDLParsers:1209 - "C:/.Xilinx/randomnumber/top.vhd" Line 56. 
randbit: Undefined symbol (last report in this block)
ERROR:HDLParsers:3324 - "C:/.Xilinx/randomnumber/top.vhd" Line 56. IN 
mode Formal randbit of randtosequence with no default value must be 
associated with an actual value.
ERROR:HDLParsers:3312 - "C:/.Xilinx/randomnumber/top.vhd" Line 57. 
Undefined symbol 'LED1'.
ERROR:HDLParsers:1209 - "C:/.Xilinx/randomnumber/top.vhd" Line 57. LED1: 
Undefined symbol (last report in this block)

I don't understand why they are undefined, haven't i defined them??

: Edited by Moderator
Author: qnd (Guest)
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')' is misplaced.

Author: Lothar Miller (lkmiller) (Moderator)
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Additionally in VHDL '=>' is much different from '<='...

Author: John Mayer (215)
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Could you specifiy where the missing ) is???

and what do mean by much different..

Isnt a => B , saying that B has the value of a
and a<= B says that a has the value of B

or am I wrong?

Author: Lothar Miller (lkmiller) (Moderator)
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John Mayer wrote:
> Could you specifiy where the missing ) is???
Of course, but to give you a little bit of a learning effect you will 
have to find this yourself. Two little hints:
1. It is somewhere in the lines 56 and 57.
2. How many ports has randtosequence? How many did you connect?

> Isnt a => B , saying that B has the value of a
> and a <= B says that a has the value of B
> or am I wrong?
Yes, you are. In no VHDL literature you will find that definition. And 
in a port list there only one of the two arrows allowed.

: Edited by Moderator
Author: John Mayer (215)
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Ok.. i correct my mistakes, i've generated the program file, but nothing 
appears to happen on the board.
entity top is
    Port ( CLock : in  STD_LOGIC;
           LED : out STD_LOGIC_vector(3 downto 0);
           Switch : in  STD_LOGIC
       );
end top;
architecture Behavioral of top is
Signal nummer: std_logic_vector (1 downto 0);

component randomnumber 
port (
      clk : in std_logic;
      gameon: in std_logic;
      bittet: out std_logic_vector (1 downto 0)
    );
end component;
component randtosequence
Port (
        LED1 : out  STD_LOGIC_VECTOR (3 downto 0);
        randbit : in  STD_LOGIC_VECTOR (1 downto 0)
    );
end component;

begin
randomnumber1 : randomnumber port map(clk => Clock, gameon => Switch, bittet => nummer); 
rantosequence1: randtosequence port map(LED1 => LED, randbit => nummer);
end Behavioral;

I've tested each module individually, and the work.
So something must be wrong on how I've connected it.

Gameon is just (on/off switch for the game)
bittet is generate psuedo random number (std_logic_vector(1 downto 0)) 
using a LFSR.
LED1 is just the LED on the board.
randbit interprets the bittet, and convert to sequence which the LED 
displays...

Author: Lothar Miller (lkmiller) (Moderator)
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John Mayer wrote:
> i've generated the program file
What does the simulation of the complete design say?

> on the board.
Which one?

> So something must be wrong on how I've connected it.
How did you assign the FPGA pins to your top level entity ports?

Author: John Mayer (215)
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No errors or warnings.

This is the board
http://www.digilentinc.com/Products/Detail.cfm?Nav...


Yes, my port declarations is of the ports in top module.
NET "LED"          LOC = "J14";
NET "gameon"              LOC = "G18";
NET "CLK"        LOC = "B8";

Author: Lothar Miller (lkmiller) (Moderator)
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There are some mismatches!
These are four pins:
> LED : out STD_LOGIC_vector(3 downto 0);
This is one pin:
> NET "LED" LOC = "J14"
And there is no gameon in the port of your top level entity:
> NET "gameon" LOC = "G18";

Pls post your VHDL file(s) and your UCF file for having a look at it...

Author: John Mayer (215)
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Ahh.. sorry

I gave you the wrong one..

  NET "switch" LOC = "G18";
  NET "LED<3>"  LOC = "R4";
  NET "LED<2>"  LOC = "F4";
  NET "LED<1>"  LOC = "P15";
  NET "LED<0>"  LOC = "E17";
  NET "CLock"   LOC = "B8";


Here is my LSFR - Randomnumber1
http://pastebin.com/SeBBtRr4
Here is my RANDOMsequence1
http://pastebin.com/CB5HQhe6

(don't worry is only few lines of code)

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