Additionally in VHDL '=>' is much different from '<='...

Could you specifiy where the missing ) is???

and what do mean by much different..

Isnt a => B , saying that B has the value of a
and a<= B says that a has the value of B

or am I wrong?

John Mayer wrote:
> Could you specifiy where the missing ) is???
Of course, but to give you a little bit of a learning effect you will 
have to find this yourself. Two little hints:
1. It is somewhere in the lines 56 and 57.
2. How many ports has randtosequence? How many did you connect?

> Isnt a => B , saying that B has the value of a
> and a <= B says that a has the value of B
> or am I wrong?
Yes, you are. In no VHDL literature you will find that definition. And 
in a port list there only one of the two arrows allowed.

Ok.. i correct my mistakes, i've generated the program file, but nothing 
appears to happen on the board.

1

entity top is

2

    Port ( CLock : in  STD_LOGIC;

3

           LED : out STD_LOGIC_vector(3 downto 0);

4

           Switch : in  STD_LOGIC

5

       );

6

end top;

7

architecture Behavioral of top is

8

Signal nummer: std_logic_vector (1 downto 0);

9

10

component randomnumber 

11

port (

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      clk : in std_logic;

13

      gameon: in std_logic;

14

      bittet: out std_logic_vector (1 downto 0)

15

    );

16

end component;

17

component randtosequence

18

Port (

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        LED1 : out  STD_LOGIC_VECTOR (3 downto 0);

20

        randbit : in  STD_LOGIC_VECTOR (1 downto 0)

21

    );

22

end component;

23

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begin

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randomnumber1 : randomnumber port map(clk => Clock, gameon => Switch, bittet => nummer); 

26

rantosequence1: randtosequence port map(LED1 => LED, randbit => nummer);

27

end Behavioral;

I've tested each module individually, and the work.
So something must be wrong on how I've connected it.

Gameon is just (on/off switch for the game)
bittet is generate psuedo random number (std_logic_vector(1 downto 0)) 
using a LFSR.
LED1 is just the LED on the board.
randbit interprets the bittet, and convert to sequence which the LED 
displays...

John Mayer wrote:
> i've generated the program file
What does the simulation of the complete design say?

> on the board.
Which one?

> So something must be wrong on how I've connected it.
How did you assign the FPGA pins to your top level entity ports?

No errors or warnings.

This is the board
http://www.digilentinc.com/Products/Detail.cfm?NavTop=2&NavSub=451&Prod=NEXYS2&CFID=4697254&CFTOKEN=4c18b30037a8e895-F722082E-5056-0201-02AE9233606926E0


Yes, my port declarations is of the ports in top module.
NET "LED"          LOC = "J14";
NET "gameon"              LOC = "G18";
NET "CLK"        LOC = "B8";

There are some mismatches!
These are four pins:
> LED : out STD_LOGIC_vector(3 downto 0);
This is one pin:
> NET "LED" LOC = "J14"
And there is no gameon in the port of your top level entity:
> NET "gameon" LOC = "G18";

Pls post your VHDL file(s) and your UCF file for having a look at it...

Ahh.. sorry

I gave you the wrong one..

  NET "switch" LOC = "G18";
  NET "LED<3>"  LOC = "R4";
  NET "LED<2>"  LOC = "F4";
  NET "LED<1>"  LOC = "P15";
  NET "LED<0>"  LOC = "E17";
  NET "CLock"   LOC = "B8";


Here is my LSFR - Randomnumber1
http://pastebin.com/SeBBtRr4
Here is my RANDOMsequence1
http://pastebin.com/CB5HQhe6

(don't worry is only few lines of code)