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Forum: FPGA, VHDL & Verilog case port map


Author: bob (Guest)
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Hi all!

I have an idea for a code I am writing but I don't know if it's 
possible. Let me explain:

I want to connect a component with an other in function of a signal.
A thing like this:

case wave_type is

       when sinus =>  V_pos: sinus_wave generic map();
                                        port map();

                      V_neg: sinus_wave generic map();
                                        port map();

       when square => V_pos: square_wave generic map();
                                         port map();

                      V_neg: square_wave generic map();
                                         port map();

      when ..........etc


I have tested that but a signal expression is expected instead of port 
map...

Do you know a solution to get what I want? Thank you

Author: ChristophZ (Guest)
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If you would like to change the component used in your code when your 
design is synthesized then you can achieve it with the "generate" 
statement.

If you would like to change the used component during runtime (when your 
hw is running) you need to instantiante all components and you need a 
multiplexer to select the desired output (for example with a case 
statement like in your code).

Author: bob (Guest)
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ChristophZ wrote:
> If you would like to change the component used in your code when
> your
> design is synthesized then you can achieve it with the "generate"
> statement.
>
> If you would like to change the used component during runtime (when your
> hw is running) you need to instantiante all components and you need a
> multiplexer to select the desired output (for example with a case
> statement like in your code).

It's for simulation only. Can you explain what you mean by "generate" 
statement please?

Author: ChristophZ (Guest)
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One of the first links my search engine presented me:
http://vhdl.renerta.com/mobile/source/vhd00033.htm

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