Forum: FPGA, VHDL & Verilog step time simulation

Author: angelo (Guest)
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Hi all,

I'm stuck on a simple issue but can't get out of it: I would like to 
generate severals waveform signals for my future testbench but the 
frequency of my signals are not correct.

Below is the code I want to simulate:
library ieee;
use ieee.std_logic_1164 .all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;

entity triangle_generator is

 generic(AMP: real;
  OFFSET: real;
  FREQ: real;
  PHASE :real);
 port(wave1: out real);
end triangle_generator;

architecture archi of triangle_generator is

signal tmp1 : real := 0.0;


 constant delta   : real := 1000.0e-12;
 constant fin  : time := 1000 ps;
 variable angle   : real := 0.0;
 variable t    : real := 0.0;
 variable PHASE_RAD : real := 0.0;
   PHASE_RAD := (math_2_pi * PHASE)/360.0;

   angle   := math_2_pi * FREQ * t;
   t := t + delta;
   tmp1 <= OFFSET+(AMP/2.0)*(2.0/math_pi)*arcsin(sin(angle));

   wait for fin;
  end loop;
 end process P1;
 wave1 <= tmp1;
end archi;

When I simule this code with FREQ=100 000 000 Hz I get the waveform in 
attachment, not really what I wanted. So I was thinking, if I write 
delta = 1000.0e-15 maybe it will be right, but absolutly not. When I 
change the value of delta, the frequency of the waveform is wrong.

So can you help me to get through this please?

Author: Lothar Miller (lkmiller) (Moderator)
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angelo wrote:
> When I change the value of delta, the frequency of the waveform is
> wrong.
You are turning the wrong screw...

Think about this:
 constant fin  : time := 1000 ps;
     wait for fin;
What is the cycle time of 100MHz?
How many 1ns steps will fit in 10ns?
Do you find any coincidence with your screenshot?

: Edited by Moderator
Author: angelo (Guest)
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Hi! Thanks! Your advices help me a lot.


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