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Forum: FPGA, VHDL & Verilog regarding for loop in counter of verilog


Author: Sarvani Nainala (sarvani)
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Hi
i want a verilog code for a counter which should count 16 clock pulses 
so that the load should become zero when it start counting and should 
become high when completion of 16 clock pulses,remain high for a next 
pulse and again should become low when the counter starts counting with 
respect to reset.Finally this should happen for 8 times
plz help me out as soon as possible.

Author: PittyJ (Guest)
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Why do you want such a code?
Why do you not code it yourself?

Author: Sarvani Nainala (sarvani)
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i need it for my project
i can't make it out plzz help me out

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