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Forum: FPGA, VHDL & Verilog Vmax not reached


Author: angelo (Guest)
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Hi everyone,

I'm writing a code for a triangular wave generator in vhdl, and I have a 
little issue. I want a signal with Vmax =3.3V and I never reach this 
value, the max is 3.2999...
There is not a really big difference but may will be damaging for what I 
want to simulate with this signal (14 bits ADC).
Do you have any hint to get exactly the 3.3 value, if is it possible?

Thank you!

My code is below:
library ieee;
use ieee.std_logic_1164 .all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;

entity test is

  generic(AMP: real;
    OFFSET: real;
    FREQ: real);
  
  port(triangle: out real);
  
end test;

architecture archi of test is

signal tmp : real := 0.0;

begin

  P1:process
  
  constant delta   : real := 1000.0e-12;
  constant fin   : time := 1000 ps;
  
  variable t   : real := 0.0;
  variable Vmax    : real := AMP/2.0;
  
  begin
  
    loop
      
      t := t + delta;
      tmp <= OFFSET+Vmax*(2.0/math_pi)*arcsin(sin(math_2_pi*FREQ*t));
      wait for fin;
    
    end loop;
    
    wait;
    
  end process P1;
  
  triangle <= tmp;
  
end archi;

Author: Duke Scarring (Guest)
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angelo wrote:
> code for a triangular wave generator in vhdl
Do you want to synthesize the code for a FPGA or just simulating?

Duke

Author: angelo (Guest)
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Hi!

Duke Scarring wrote:
> Do you want to synthesize the code for a FPGA or just simulating?

Just simulating

Author: Duke Scarring (Guest)
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angelo wrote:
> I never reach this value, the max is 3.2999
3.2999 is the same as 3.30 but its not expressible with binary digits.
It's the same as 0.5 in binary, a periodic fraction.

Duke

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