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Forum: FPGA, VHDL & Verilog RAM overflow is it acceptable


Author: Abdallah      (Company: Home) (my_name)
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Peace!
I use a RAM of (64*64)*8bits ,
this is shoot screan of results:
is it acceptable!!!

Number of Slices  :            21352 from 13312    ------->160%
Number of Slice Flip Flops  :  32801 from 26624    -------> 123%
Number of 4 input LUTs  :      29767 from 26624    -------> 111%
Number of bonded IOBs  :       33 from 221            -------> 14%
Number of GCLKs  :             2 from 8                ------->25%
------------------------------------------------------------------------ 
---
this is the entity that I use:
entity writeRam64_64 is
 port( clk:in std_logic;   --Clock
       rst : in std_logic; --Reset
       tram_in : in std_logic_vector(7 downto 0);  -- 8bits In to be
stocked in the RAM   //to write RAM
       tram_in_pret : in std_logic;  --  8bits are ready to stock
       bus_adrB:in std_logic_vector(12 downto 0);  -- receive the 
adresse
want its value //to read RAM
       tram_outB : out std_logic_vector(7 downto 0); -- send the
adresse'value read
       RamB_pret : out std_logic); -- adresse'value read  is ready
end writeRam64_64;

and this is the RAM divided to 4 Blocks

type RAM is array (1 to 1024) of std_logic_vector(7 downto 0);
signal RamB1,RamB2,RamB3,RamB4 : RAM;

THANK YOU!

Author: Lothar Miller (lkmiller) (Moderator)
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Abdallah      wrote:
> Peace!
> I use a RAM of (64*64)*8bits ,
> this is shoot screan of results:
> is it acceptable!!!
If that is a question, then the answer is: No! Simply because it won't 
fit in your FPGA.

But you should read the manual of your particular toolchain and have a 
look for the synthesis guide to get a Block RAM instead of distributed 
RAM.

Author: Abdallah      (Company: Home) (my_name)
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Lothar Miller wrote:
> If that is a question, then the answer is: No! Simply because it won't
> fit in your FPGA.
Actually the question is: does a RAM of (64*64)*8bits should reserve all 
these resources?

> But you should read the manual of your particular toolchain and have a
> look for the synthesis guide to get a Block RAM instead of distributed
> RAM.

I didn't get the meaning of ""get a Block RAM instead of distributed 
RAM.""
can you explain more, or give me some documentation

Author: Lothar Miller (lkmiller) (Moderator)
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Abdallah      wrote:
> Actually the question is: does a RAM of (64*64)*8bits should reserve all
> these resources?
If you have the wrong hardware description, then your RAM is not 
instantiated as a RAM block, instead a lot of Lookup-Tables (LUT) are 
used.

>> But you should read the manual of your particular toolchain and have a
>> look for the synthesis guide to get a Block RAM instead of distributed
>> RAM.
> I didn't get the meaning of ""get a Block RAM instead of distributed
> RAM."" > can you explain more, or give me some documentation
Do you have access to Google, that search engine on the internet?
If so, then just enter some keywords like "vhdl block ram distributed 
ram", and I'm pretty sure you will find the Data Sheet of your 
particular FPGA and the Users Guide of your particular synthesizer. Lets 
assume, both of them were Xilinx, then you could try something like 
this:
https://www.google.de/search?q=vhdl+block+ram+dist...
https://www.google.de/search?q=synthesizer+users+g...

As an alternative you can dig around at the Xilinx website:
http://www.xilinx.com/support/documentation/sw_man...

Author: Abdallah      (Company: Home) (my_name)
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thank you  Lothar Miller , It's done and work successful
I used the core generator to generate BRam of 4096*8bits, and i's work . 
thank you again

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