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Forum: FPGA, VHDL & Verilog Beginner problems Syntax error


Author: John Mayer (215)
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I am trying to make a DEC to 7 segment converter for 2 segment, but i am 
having some problems with the syntax.
signal counter_1r: std_logic_vector (7 downto 0);
signal counter_1: integer range 0 to 9;
counter_1r  <= "11000000" when counter_1 = 0 else
        <= "11111001" when counter_1 = 1 else
        <= "10100100" when counter_1 = 2 else
        <= "10110000" when counter_1 = 3 else
        <= "10011001" when counter_1 = 4 else
        <= "10010010" when counter_1 = 5 else
        <= "10000010" when counter_1 = 6 else
        <= "11111000" when counter_1 = 7 else
        <= "10000000" when counter_1 = 8 else
        <= "10010000" when counter_1 = 9 else
        "00000000";
I am getting a error message saying that there is a syntax error near 
"<="..
Which i don't get.  Counter_1 is getting incremented, and counter_1r 
runs concurrently, (not in a process).

So why am i getting this error?

Author: Jan M. (mueschel)
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There's no '<=' allowed after each of the 'else':
counter_1r  <= "11000000" when counter_1 = 0 else
        "11111001" when counter_1 = 1 else
        ...

Author: John Mayer (215)
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Thanks alot :)

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