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Forum: FPGA, VHDL & Verilog Trying to divide 100Mhz clock to 25Mhz for VGA


Author: Darren Rodriguez (Guest)
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I came up with this but I am not sure if this will give me 25Mhz and I 
can't think of a way to test it. Can someone tell me if this is right?
 signal clock_25MHz : std_logic;
  signal counter : integer;
  
  process(clk,counter,clock_25Mhz)
    constant max_count : integer := 3; --divide 100 by 4 (0-3)
  begin
    if (rising_edge(clk)) then
      counter <= counter + 1;
        if (counter = max_count) then
          clock_25Mhz <= not clock_25Mhz;
          counter <= 0;
        end if;
    end if;
  end process;

Author: Ottmar (Guest)
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Darren Rodriguez wrote:
> I
> can't think of a way to test it

You may try simulation ...

Author: Lothar Miller (lkmiller) (Moderator)
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Darren Rodriguez wrote:
> Can someone tell me if this is right?
No, it isn't. A clock is not generated by toggling a flipflop. To 
generate a real clock you must use one of the clock managers in your 
FPGA.

BTW: which one?

Author: ... (Guest)
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Altera Quartus will promote clock_25 automatically to the clock network
if clock_25 is used as clock for other parts. No need for BUFG.

But clock_25 should not be a part of the sensitiv list of the process.

Author: 'ingenieur d route (Guest)
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this is the most xxxx way to generate a clock I have ever seen.

... wrote:
> But clock_25 should not be a part of the sensitiv list of the process.
why not?

Author: Lothar Miller (lkmiller) (Moderator)
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The only necessary signal in the sensitivity list of this synchronous 
process is clk.

: Edited by Moderator
Author: Achim S. (Guest)
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I don't know, if on Altera Quartus this will feed a clock network as 
...Guest states or if it will be just a toggling flip-flop.

But I'm quite sure that clk_25 will run at 12.5MHz, not at 25MHz ;-)

Author: ... (Guest)
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> But I'm quite sure that clk_25 will run at 12.5MHz, not at 25MHz

The TO can use a PLL to get a 200 MHz clock.

Or he divides by two only...

Author: Lothar Miller (lkmiller) (Moderator)
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... wrote:
> Or he divides by two only...
Or he uses a binary counter and takes the third bit of it:
   signal cnt : unsigned( 2 downto 0) := "000";
 :
   clkcnt <= clkcnt+1 when rising_edge(clk); -- take advantage of the automatic rollover of an unsigned vector
   clock_25 <= clkcnt(2);

Achim S. wrote:
> I don't know, if on Altera Quartus this will feed a clock network as
> ...Guest states
And up to now its not known if it is a FPGA at all and if it is one if 
it is from Altera...

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