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Forum: FPGA, VHDL & Verilog what can i do?


Author: tanko (Guest)
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hi every one....

i have a design measure the distance between two samples (inputs),
d(s1,s2). and i want to ask a question


if i have 4 samples such as [ s1,s2,s3,s4 ] and i want to get the 
distances between every two samples, then i would have 
d(s1,s2),d(s1,s3),d(s1,s4),d(s2,s3),d(s2,s4)and d(s3,s4).
what should i do 1 or 2

1- should i repeat that module 6 times and i would have 6 component of 
it connected together to get the 6 distances between every sample and 
the other ...or

2- should i use that module one time and store the distance in register 
and reset the module then measure the distance between the next two 
samples and store the the result in another register again and so on....

 because i will need the distances result for sum them all.

thanks for help.

Author: PittyJ (Guest)
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Do 1

Author: Lothar Miller (lkmiller) (Moderator)
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tanko wrote:
> because i will need the distances result for sum them all.
In this case the distance must be
dtot = 3 x d(s1,s4) + d(s2,s3)
because
d(s1,s4) = d(s1,s2) + d(s2,s4) = d(s1,s3) + d(s3,s4)
and therefore
dtot = d(s1,s4) + d(s1,s2)+d(s2,s4) + d(s1,s3)+d(s3,s4) + d(s2,s3)

Author: tanko (Guest)
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Lothar Miller wrote:

> In this case the distance must be
> dtot = 3 x d(s1,s4) + d(s2,s3)
> because
> d(s1,s4) = d(s1,s2) + d(s2,s4) = d(s1,s3) + d(s3,s4)
> and therefore
> dtot = d(s1,s4) + d(s1,s2)+d(s2,s4) + d(s1,s3)+d(s3,s4) + d(s2,s3)

sorry i didn't get your remark well
the four samples s1,s2,s3,s4
different and the distances results would e different

Author: Lothar Miller (lkmiller) (Moderator)
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tanko wrote:
> different and the distances results would e different
If the distances are in ascending od descending order from s1 to s4 then 
my suggestion will work. Otherwise it will be more complcated...

Author: tanko (Guest)
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Lothar Miller wrote:

> If the distances are in ascending or descending order from s1 to s4 then
> my suggestion will work. Otherwise it will be more complicated...

no lother distances would not e ascending or descending order it will e 
completely different ,so would you suggest to do 1 or 2 as pittyj

Author: Lothar Miller (lkmiller) (Moderator)
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Take solution 1 if you have enough ressources on the FPGA.

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