Forum: FPGA, VHDL & Verilog solution for large memory requirement for FPGA

Author: Vinayak S. (vinayak_s)
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I am designing "time interleaver" for DVB-T2, which is require large 
memory to be store before interleave.
Means, 32400 values in a one row and like that 1024 column of data need 
to be store before doing operation.

32400 rows, 1024 columns and each location of 17-bits wide.

32400  1024  17-bits = 564019200 bits need to be store....

What is the solution for this to be done.......?

I am using Spartan 3A-DSP........

Author: Duke Scarring (Guest)
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Just use external attached dynamic memory...



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