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Forum: FPGA, VHDL & Verilog How to include deadtime in pwm generator


Author: Tosin Akin (Company: mearch) (tosin)
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Hi,

I am looking to control a H-bridge with a PWM which I have generated in 
my code, however I am clueless on how to include a dead timing in the 
PWM. I need a deadtime of 750ns on the on-time and 1us off time.

Thanks.

Author: al3ko (Guest)
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How about a deadtime driver? Haven't checked your code, though there are 
some driver ICs on the market with adjustable deadtimes.

Cheers,

Author: Tosin Akin (Company: mearch) (tosin)
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al3ko wrote:
> How about a deadtime driver? Haven't checked your code, though there are
> some driver ICs on the market with adjustable deadtimes.
>
> Cheers,

Hi,

I would prefer to implement the deadtime from the fpga as that's part of 
the requirement, otherwise ICs are more convenient.

Regards.

: Edited by User
Author: Lothar Miller (lkmiller) (Moderator)
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Tosin Akin wrote:
> implement the deadtime from the fpga
Try this with google translator (its German):
http://www.lothar-miller.de/s9y/archives/58-Totzei...

Author: Tosin Akin (Company: mearch) (tosin)
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Lothar Miller wrote:
> Tosin Akin wrote:
>> implement the deadtime from the fpga
> Try this with google translator (its German):
> http://www.lothar-miller.de/s9y/archives/58-Totzei...

Thank you for that link. Unfortunately the code is in VHDL, is there a 
way to modify it to verilog please? as I am working with verilog.

Author: Lattice User (Guest)
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Tosin Akin wrote:

> Thank you for that link. Unfortunately the code is in VHDL, is there a
> way to modify it to verilog please? as I am working with verilog.

There are some free VHDL to Verilog translators out there, just google 
for it.

But Lothars sample isn't that big, it is no biggie to do that from hand, 
and have then the benefit to understand how it is working.

Author: Lothar Miller (lkmiller) (Moderator)
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Tosin Akin wrote:
> is there a way to modify it to verilog please?
No problem: understand the idea and after a few moments you will see 
what you have to write down in Verilog...

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