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Forum: FPGA, VHDL & Verilog quick response: please help me to clear the warnings


Author: Padma Baskaran (Company: CIET) (padma)
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hi
i have some queries.please help me to rectify.
how to synthesis a program in verilog with clock input without using 
test bench.

every time we synthesis our code we get

" Minimum period: No path found Minimum
input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: No path found"

some warnings too....

======================================================================== 
=
*                            HDL Analysis 
*
======================================================================== 
=
Analyzing top module <extension>.
INFO:Xst:2546 - "extension.v" line 45: reading initialization file 
"indataex.txt".
"extension.v" line 46: $display : incoming data
INFO:Xst:2546 - "extension.v" line 51: reading initialization file 
"insignex.txt".
ERROR:Xst:2353 - "extension.v" line 51: Address 50 is invalid in call of 
system task $readmemb.
"extension.v" line 52: $display : signature
ERROR:Xst:2634 - "extension.v" line 74: For loop stop condition should 
depend on loop variable or be static.
ERROR:Xst:1468 - "extension.v" line 91: Unexpected event in always block 
sensitivity list.

Found 3 error(s). Aborting synthesis.
-->

Total memory usage is 256604 kilobytes

Number of errors   :    3 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    2 (   0 filtered)


Process "Synthesize - XST" failed


i attached my coding for reference


plz plz plz help me .im in hurry to present my project

Author: Bürgerwehr (Guest)
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LOL you want to synthesize $readmemb() ? Come on.....

Author: Padma Baskaran (Company: CIET) (padma)
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plz help me to rewrite my code..plz plz

Author: Lothar Miller (lkmiller) (Moderator)
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Bürgerwehr wrote:
> LOL you want to synthesize $readmemb() ?
For me that looks like initialising an array from a file. Nothing must 
be synthesized here. But over all this code of course never ever will be 
able to be synthesized and run on an FPGA...

Padma Baskaran wrote:
> plz help me to rewrite my code..plz plz
Did you read the error messages? What happens in those lines?
Why do the line numbers in the messages not match the file?
Where did you find something like this: always @(k>0)
Why do all of your files end with *.txt and not with *.v?
Why is there absolutely no indentation in your code?
Why      reg a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15,a16;
and not  reg [1:16]a;


BTW:
This is usually not a good idea:
always @(negedge clk)
always @(posedge clk)
Good design practice for a synthesizeable design is to use only the same 
edge of the clock.

Author: Padma Baskaran (Company: CIET) (padma)
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.txt is my text file and .v is my top module

Author: Padma Baskaran (Company: CIET) (padma)
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plz help to debug my code that is my original code

Author: Arne Maximilian R. (arnemaximilian_r44)
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They already told you to change some things.
if(e7==1)
$display("incoming data in the array[%0d]=%b is matched with signature, intrusion detected",hh,insign1);
else
$display("no intrusion");
end

For example is totally wrong. You are trying to synthesis your code but 
this code is impossible to synthesis. It is only for the test bench so 
you need to remove this kind of code before you are trying to synthesis 
your project!

Author: Padma Baskaran (Company: CIET) (padma)
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i try to change my code .i got synthesis report for max time alone .help 
me get min timing report and power report



my code:

module SSS(clk,opp);
//DECLARATIONS
input clk;
output reg [15:0]opp;
reg [15:0]array1[0:127];
reg [15:0]array2[0:49];
reg [15:0]indata;
reg [15:0]insign;
reg [15:0]insign1;
reg [31:0]index[0:49];
reg [31:0]identifier;
reg a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15,a16;
reg b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15,b16;
reg c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16;
reg d1,d2,d3,d4,d5,d6,d7,d8;
reg e1,e2,e3,e4,e5,e6,e7;
integer i=0,j,k=0,l,hh,c,reset=0,flag,flag1=0,z;
wire m,n,o,p,d,e;
// INITIALIZING ARRAY TO ZERO
initial
begin
for(l=0;l<50;l=l+1)
index[l]=32'b0;
end
//READING AN INCOMING DATA FILE FROM ARRAY1
initial
begin
$readmemb("indataex.txt",array1);
for(z=0;z<128;z=z+1)
$display("array1[%0d]=%b",z,array1[z]);
end
//INPUT POSEEDGE OF CLOCK
always@(posedge clk)
begin
opp <= array1[z];
end
//READING A SIGNATURE DATA FILE FROM ARRAY2
initial
begin
$readmemb("insignex.txt",array2);
for(z=0;z<50;z=z+1)
$display("array2[%0d]=%b",z,array2[z]);
end
//COMPARING MSB BITS OR PREFIX MATCHING
initial
begin
for(j=0;j<50;j=j+1)
begin
insign=array2[j];
if(flag==1)
begin
if (indata != 16'b0)
begin
if(indata[15:12] == insign[15:12])
begin
index[k]=j;
//$display("index [%0d]=%b",k,index[k]);
k=k+1;
//flag1=1;
end
end
end
identifier=k;
end
end
//KNOWING WHICH INDEX HAS MATCHED
initial
begin
if(identifier>0)
begin
if (indata != 16'b0)
begin
for(c=0;c<50;c=c+1)
begin
if(c<identifier)
begin
hh=index[c];
insign1=array2[hh];
//$display("the prefix matched: array value is array2[%0d] 
=%b",hh,insign1);
//SUFFIX MATCHING OR LSB BITS
if(indata[3:0]==insign1[3:0])
begin
//$display("the suffix matched: array value is array2[%0d] 
=%b",hh,insign1);
//COMPARING CENTRE BITS
if(indata[9:6]==insign1[9:6])
begin
//$display("the centre bits matched: array value is array2[%0d] 
=%b",hh,insign1);
//16 BIT INCOMING DATA
a1 = insign1[0];
a2 = insign1[1];
a3 = insign1[2];
a4 = insign1[3];
a5 = insign1[4];
a6 = insign1[5];
a7 = insign1[6];
a8 = insign1[7];
a9 = insign1[8];
a10 = insign1[9];
a11 = insign1[10];
a12 = insign1[11];
a13 = insign1[12];
a14 = insign1[13];
a15 = insign1[14];
a16 = insign1[15];
//16 BIT MATCHED SIGNATURE (PREFIX ,SUFFIX AND CENTRE BITS)
b1 = indata[0];
b2 = indata[1];
b3 = indata[2];
b4 = indata[3];
b5 = indata[4];
b6 = indata[5];
b7 = indata[6];
b8 = indata[7];
b9 = indata[8];
b10 = indata[9];
b11 = indata[10];
b12 = indata[11];
b13 = indata[12];
b14 = indata[13];
b15 = indata[14];
b16 = indata[15];
//FILTER USING XNOR GATE
c1= (~a1 & ~b1)|(a1 & b1);
c2= (~a2 & ~b2)|(a2 & b2);
c3= (~a3 & ~b3)|(a3 & b3);
c4= (~a4 & ~b4)|(a4 & b4);
c5= (~a5 & ~b5)|(a5 & b5);
c6= (~a6 & ~b6)|(a6 & b6);
c7= (~a7 & ~b7)|(a7 & b7);
c8= (~a8 & ~b8)|(a8 & b8);
c9= (~a9 & ~b9)|(a9 & b9);
c10= (~a10 & ~b10)|(a10 & b10);
c11= (~a11 & ~b11)|(a11 & b11);
c12= (~a12 & ~b12)|(a12 & b12);
c13= (~a13 & ~b13)|(a13 & b13);
c14= (~a14 & ~b14)|(a14 & b14);
c15= (~a15 & ~b15)|(a15 & b15);
c16= (~a16 & ~b16)|(a16 & b16);
// COMBINING OUTPUT FROM XNOR GATE TO AND GATE
d1 = c1 & c2;
d2 = c3 & c4;
d3 = c5 & c6;
d4 = c7 & c8;
d5 = c9 & c10;
d6 = c11 & c12;
d7 = c13 & c14;
d8 = c15 & c16;
e1 = d1 & d2;
e2 = d3 & d4;
e3 = d5 & d6;
e4 = d7 & d8;
e5 = e1 & e2;
e6 = e3 & e4;
opp = e5 & e6;
end
else
opp=0;
end
else
opp=0;
end
end
end
if(c==identifier)
identifier=32'b0;
end
end
endmodule




reply me soon plzz... i m in hurry......

Author: Lattice User (Guest)
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for loops in VHDL/verilog don't behave as in C!

The synthesiser creates parallel hardware for each iteration of the 
loop, resulting in a big resource hungry and slow design.

BTW your code is unreadable. Wse indentation!

Author: Bürgerwehr (Guest)
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Did you ever read any book about verilog for hardware design? your 
entire module is a piece of crap. sorry for that but you definitely need 
to start at the beginning!!! you will never ever get this running on a 
fpga....

Author: Padma Baskaran (Company: CIET) (padma)
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whch type of book i should use ... now i m using palanithkar on verilog 
coding......

Author: Lothar Miller (lkmiller) (Moderator)
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Padma Baskaran wrote:
> now i m using palanithkar on verilog coding......
That looks ok. Read and understand it. And have in mind that only a 
very little part of Verilog can be synthesized on hardware. Most of the 
language is for simulation only!

Author: Padma Baskaran (Company: CIET) (padma)
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hi sir,


 i request you to help me. because i am running out of time . i hv only 
to more days to submit my project . plz some one re write my code..... 
plzzzz plzzz plzzzz... i tried my level best .... i started to learn 
...but these no time for me .....plz help me

Author: Bürgerwehr (Guest)
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Padma Baskaran wrote:
> hi sir,
>
>  i request you to help me. because i am running out of time . i hv only
> to more days to submit my project . plz some one re write my code.....
> plzzzz plzzz plzzzz... i tried my level best .... i started to learn
> ...but these no time for me .....plz help me

It is not possible to rewrite this module in a few minutes because your 
approach to solve this task is not designed for hardware synthesis!

FYI: http://www.asic-world.com/verilog/synthesis2.html

Author: Padma Baskaran (Company: CIET) (padma)
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please tell some other solution......

Author: Padma Baskaran (Company: CIET) (padma)
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is there any tool to convert my simulated code to synthesis-able code..
plz reply me soon....

Author: Arne Maximilian R. (arnemaximilian_r44)
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Padma Baskaran wrote:
> is there any tool to convert my simulated code to synthesis-able
> code..
> plz reply me soon....

There is a way to convert synthesis-able code into code for the 
simulation.

I understand that you have a problem with the time, but you're asking us 
to read your long code, understand it and than fix it?
The really best thing to do would be starting new from scratch.

Also it's not helpful for a helping person to read something like this:
c1= (~a1 & ~b1)|(a1 & b1);
c2= (~a2 & ~b2)|(a2 & b2);
c3= (~a3 & ~b3)|(a3 & b3);
c4= (~a4 & ~b4)|(a4 & b4);
c5= (~a5 & ~b5)|(a5 & b5);
c6= (~a6 & ~b6)|(a6 & b6);
c7= (~a7 & ~b7)|(a7 & b7);
c8= (~a8 & ~b8)|(a8 & b8);
c9= (~a9 & ~b9)|(a9 & b9);
c10= (~a10 & ~b10)|(a10 & b10);
c11= (~a11 & ~b11)|(a11 & b11);
c12= (~a12 & ~b12)|(a12 & b12);
c13= (~a13 & ~b13)|(a13 & b13);
c14= (~a14 & ~b14)|(a14 & b14);
c15= (~a15 & ~b15)|(a15 & b15);
c16= (~a16 & ~b16)|(a16 & b16);

Please use the simple bus operations to short the code and make it 
readable.
Example: Using a, b and c as bus signals.
c= (~a & ~b)|(a & b);
Same function but readable.

Author: Padma Baskaran (Company: CIET) (padma)
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i didnt get u..........

Author: Lothar Miller (lkmiller) (Moderator)
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Padma Baskaran wrote:
> i didnt get u....
Thats the problem.
I did, although I have no deeper knowledge of Verilog...

Padma Baskaran wrote:
> is there any tool to convert my simulated code to synthesis-able code..
That tool is in between your ears: its called brain.

Padma Baskaran wrote:
> please tell some other solution....
Ask a classmate of yours to sit together with this particular task. This 
can't be done from remote...

Author: Padma Baskaran (Company: CIET) (padma)
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hi sir ,
   i tried some thing in my code and i get the min time plz help me to 
get the power report plzzz . here by i insert my code...... plz reply 
soon..plzzzz

Author: Lothar Miller (lkmiller) (Moderator)
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Lothar Miller wrote:
> Why do all of your files end with *.txt and not with *.v?
And now you post a potentially virulent *.docx file? I (and lots of 
others) will not open such a file. Do you read the answers to your posts 
at all? If you do: do you try to understand them?

You must do the work on your own. Maybe some can help you if you ask a 
specific question. Keep in mind: YOU are running out of time, not anyone 
of us.

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