Forum: µC & Digital Electronics Problem in the power on of a system bases in a FPGA + uc

Author: Enrique Perez (flote21)
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I am breaking my head with the start up of a system based in a SPARTAN3 
FPGA and one PIC18F4520.

One reset push button is conected to the FPGA. when I push this RESET 
button, the FPGA is reset and the uC is also reset by the FPGA. 
Everything is working fine in the uC and in the FPGA. However in the 
power on of the system. Everything is also working fine, but the uC miss 
the reset command sent by the FPGA. this reset command is read ok when I 
press the reset button...

The communication between the FPGA and the uC is based in the signals: 
hand and shake and one data bus of 8 bits. I play with "hand" and 
"shake" to have a success communication...

I figure out that maybe I have to wait for the uC to be ready for 
receiving some command. Maybe I have to implement a delay in the FPGA of 
3sec and after that send the command to the uC....

Any idea about how to solve the power-on system problem??


Author: Easylife (Guest)
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Maybe your reset phase the FPGA generates is too short.
You could look up the required timing in the datasheet, or as a rule of 
thumb, just try 1ms.
After resetting, you have to wait a while until you could communicate 
with your uC, as it needs to boot up.
To find out the boot time, your first instruction could be "set port x 
to high". Then you could measure the required time between RESET going 
high to port x going high.


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