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Forum: FPGA, VHDL & Verilog dividing clock


Author: Bilel (Guest)
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Salut tout le monde , j`'ai un problème avec mon code. Mon but est 
d,obtenir une horloge de période 2s.
voila mon code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
 use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_enabler is
    Port ( clk_100Mhz : in  STD_LOGIC;
           new_clk : out  STD_LOGIC);
end clk_enabler;

architecture clockenabler of clk_enabler is

  signal prescaler : std_logic_vector(25 downto 0);
  signal clk_2s : std_logic;
begin

  gen_clk : process (clk_100Mhz)
  begin  -- process gen_clk

      clk_2s   <= '0';
      prescaler   <= (others => '0');

   if rising_edge(clk_100Mhz) then   -- rising clock edge
      if prescaler = X"BEBC200" then     -- 200000000 in hex
        prescaler   <= (others => '0');
        clk_2s   <= not clk_2s;
      else
        prescaler <= STD_LOGIC_VECTOR(unsigned(prescaler) + "1") ;
      end if;
  end if;
 end process;
 new_clk <=  clk_2s ;

 end;


L'erreur est la suivante : Signal prescaler cannot be synthesized, bad 
synchronous description. The description style you are using to describe 
a synchronous element (register, memory, etc.) is not supported in the 
current software release.
S'il vous plait j'ai besoin d'aide

Author: Lothar Miller (lkmiller) (Moderator)
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Bilel wrote:
> S'il vous plait j'ai besoin d'aide
Simply kick out this two lines:
clk_2s <= '0';
prescaler <= (others => '0');

But this is not the way to make a clock inside a FPGA!

Author: Bilel Ben Jabeur (Guest)
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Thanks but what do you mean kick them out? retrieve them?
And this doesn't give me a clock with 0.5 htz frequency?
how do i do it?
thanks

Author: Bilel Ben Jabeur (Guest)
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I wrote this
entity Clk_enabler is
Port ( clk100M : in STD_LOGIC;
clk : out STD_LOGIC);
end Clk_enabler;
architecture Behavioral of Clk_enabler is
signal counter : integer:=0;
begin
process(clk100M)
begin
if rising_edge(clk100M) then
if (counter = 200000000) then
counter<=0;
else
counter <= counter + 1;
end if;
end if;
end process;
process(counter)
begin
if (counter = 200000000) then
clk<='1';
else
clk<='0';
end if;

end process;
end Behavioral;
but it didn't work there was an error n 200000000

Author: Lothar Miller (lkmiller) (Moderator)
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Bilel Ben Jabeur wrote:
> I wrote this
Pls embed your VHDL code in the following tokens (without spaces):
[ vhdl ]
your code
[ /vhdl ]
And use tabs and spaces to indent your code!

> I wrote this
> entity
Every VHDL description starts well before the keyword "entity"!

> but it didn't work there was an error n 200000000
And how does this error look like? Whats the error message EXACTLY?


Try that:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Clk_enabler is
  Port ( clk100M : in STD_LOGIC;
         clk : out STD_LOGIC);
end Clk_enabler;

architecture Behavioral of Clk_enabler is
  signal counter : integer RANGE 0 TO 200000000 := 0;
begin

process (clk100M) begin
  if rising_edge(clk100M) then
    if (counter = 200000000) then
      counter<=0;
      clk<='1';
    else 
      counter <= counter + 1;
      clk<='0';
    end if;
  end process;
end Behavioral;

BTW: clk MUST NOT be used as a clock! It is only an enable signal!

Author: Bilel Ben Jabeur (Guest)
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Thanks a lot. You've been really helpfull.
In my project, I need to use CLK in another source(VHDL module) :
 
if rising_edge(clk)...
Can I? (by the way I'm new at this)
How do I connect the 2 vhdl modules so that the (clk) output of the 
first one (the one you've been helping me with)can be an input for the 
second one? do I have to create another module?
Thanks again.

Author: guest (Guest)
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Have a look at clock enables. That's the way you should do it.
You shouldn't use gated clocks, that's what Lothar was talking about.

Author: Lothar Miller (lkmiller) (Moderator)
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Bilel Ben Jabeur wrote:
> Can I? (by the way I'm new at this)
Lothar Miller wrote:
> clk MUST NOT be used as a clock! It is only an enable signal!

So use it that way!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Clk_enabler is
  Port ( clk100M : in STD_LOGIC;
         clk : out STD_LOGIC);
end Clk_enabler;

architecture Behavioral of Clk_enabler is
  signal counter : integer RANGE 0 TO 200000000 := 0;
  signal twoseconds : std_logic := '0';
begin

process (clk100M) begin
  if rising_edge(clk100M) then
    if (counter = 200000000) then
      counter<=0;
      twoseconds <='1';
    else 
      counter <= counter + 1;
      twoseconds <='0';
    end if;
  end process;
end Behavioral;


process (clk100M) begin
  if rising_edge(clk100M) then -- the one and only clock in the design!!!!
    if (twoseconds ='1') then  -- this is a clock enable
       ...

: Edited by Moderator
Author: Bilel Ben Jabeur (Guest)
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I really am new at this. My project is a system fot street lights.
First step : divide the clock in the first vhdl module, as Lothar said :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Clk_enabler is
  Port ( clk100M : in STD_LOGIC;
         clk : out STD_LOGIC);
end Clk_enabler;

architecture Behavioral of Clk_enabler is
  signal counter : integer RANGE 0 TO 200000000 := 0;
begin

process (clk100M) begin
  if rising_edge(clk100M) then
    if (counter = 200000000) then
      counter<=0;
      clk<='1';
    else 
      counter <= counter + 1;
      clk<='0';
    end if;
  end process;
end Behavioral;

Second step is my state machine in the second module.
Here it is
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity main is
    Port ( BI : in  STD_LOGIC;
           ABP : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           SA : out  STD_LOGIC;
           FPTP : out  STD_LOGIC;
           FPV : out  STD_LOGIC;
           FPO : out  STD_LOGIC;
           FPR : out  STD_LOGIC;
           FSV : out  STD_LOGIC;
           FSO : out  STD_LOGIC;
           FSR : out  STD_LOGIC);
end main;
architecture Behavioral of main is
signal counter: NUMERIC_STD;
signal FPV1 :   STD_LOGIC;
signal FPO1 :   STD_LOGIC;
signal FPR1 :  STD_LOGIC;
signal FSV1 :  STD_LOGIC;
signal FSO1 :   STD_LOGIC;
signal FSR1 :   STD_LOGIC;
signal SA1 :  STD_LOGIC;
signal FPTP1 :   STD_LOGIC;
begin
process(clk, BI)
begin
   if rising_edge(clk) then
    if (BI='1') then
              counter <= 0 ;
    elsif (counter >=0 and counter<9) or (counter = 10)  then
         counter <= counter +1 ;
    end if;
   end if;  
end process;  
process(BAP)
begin
     if (BAP='1') then
          SA1 <= '1' ;
     end if;     
end process;
SA <= SA1;
process(SA1)
begin
if counter=9 then
    if SA1=('1')then
      FPTP1 <= '1';
            SA1 <= '0' ;
            counter <= counter+1 ;
    else counter <= 0 ; 
    end if;   
end if;   
end process;
SA <= SA1;
FPTP <= FPTP1 ;
 
 process
 begin
if (counter=11) then
      FPTP1 <= '0';
      counter <= 0;
end if;
end process;
FPTP <= FPTP1 ;
process
begin
if (counter=0) then
        FPV1 <=  '1' ;
  FPO1 <=  '0' ;
  FPR1 <=  '0' ;
        FSV1 <=  '0' ;
        FSO1 <=  '0' ;
  FSR1 <=  '1' ;
elsif (counter=4) then
        FPV1 <= '0'  ;
  FPO1 <= '1'  ;
  FPR1 <= '0'  ;
        FSV1 <= '0'  ;
        FSO1 <= '0'  ;
  FSR1 <=  '1' ;      
elsif (counter=5) then
        FPV1 <=  '0' ;
  FPO1 <=  '0' ;
  FPR1 <=  '1' ;
        FSV1 <=  '1' ;
        FSO1 <=  '0' ;
  FSR1 <=  '0' ;  
elsif (counter=8) then
        FPV1 <=  '0' ;
  FPO1 <=  '0' ;
  FPR1 <=  '1' ;
        FSV1 <=  '0' ;
        FSO1 <=  '1' ;
  FSR1 <=  '0' ;  
end if;
end process;

FPV <=  FPV1 ;
FPO <=  FPO1 ;
FPR <=  FPR1 ;
FSV <=  FSV1 ;
FSO <=  FSO1 ;
FSR <=  FSR1 ;


end Behavioral;
What do I do so that (clk) the input of the second module is the output 
of the first?

Author: Lothar Miller (lkmiller) (Moderator)
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This is a combinatorial loop (aka. combinational loop):
process(SA1)
begin
if counter=9 then
    if SA1=('1')then
      FPTP1 <= '1';
            SA1 <= '0' ;
            counter <= counter+1 ;
In real life "counter" here is just a very high frequency noise 
generator. It will not do any useful things...
Simulation will look ok, because of the missing signal counter in the 
sensitivity list.

And this here is not synthesizeable at all:
process
begin
   if (counter=0) then
A process with no sensitivity list needs a "wait" statement somewhere 
inside.

And of course: you cannot drive "counter" in more than one process.

: Edited by Moderator
Author: Bilel Ben Jabeur (Guest)
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so a signal can't be be in two sensitivity lists of different processes 
?

Author: Bilel Ben Jabeur (Guest)
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can the clock be in two sensitivity lists of different processes ?

Author: guest (not op) (Guest)
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Lothar Miller wrote:
> This is a combinatorial loop (aka. combinational
> loop):process(SA1)
> begin
> if counter=9 then
>     if SA1=('1')then
>       FPTP1 <= '1';
>             SA1 <= '0' ;
>             counter <= counter+1 ;
> In real life "counter" here is just a very high frequency noise
> generator. It will not do any useful things...
> Simulation will look ok, because of the missing signal counter in the
> sensitivity list.

Could you please explain why this is a combinatorial loop? Or why 
"counter" would be incremented all the time?

I can see the problems in the posted vhdl code, but can't see the loop 
in this particular process....

Author: Lothar Miller (lkmiller) (Moderator)
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guest (not op) wrote:
> I can see the problems in the posted vhdl code, but can't see the loop
> in this particular process....
There is a counter without a clock. That's a combinatorial loop. In the 
case here it is hidden behind a incomplete sensitivity list and a 
littlte bit logic, and so it cannot easily seen in simulation. And also 
maybe the synthesizer cannot recognize it... :-(

> Or why "counter" would be incremented all the time?
In fact its far more complicated here, because the enable logic for the 
counter itself uses the counter. That can lead to very unexpected and 
strange behaviour...
So indeed "counter" will not increment all the time. I missed the "if 
counter=9".

Bilel Ben Jabeur wrote:
> so a signal can't be be in two sensitivity lists of different processes
A signal must be in a process sensitivity list if it makes the 
recalculation of that process necessary. So of course a signal can be in 
lots of sensitivity lists.
But only one process or one concurrent statement can assign a value to a 
signal.

BTW always keep in mind: the sensitivity list is ONLY for the simulator, 
it isn't used by the synthesizer at all!

: Edited by Moderator

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